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hc05h12grs/d rev. 1.0 non-disclosure agreement required 68hc(7)05h12 general release specification rev. 1.0 november, 1998
non-disclosure agreement required general release speci?ation general release specification mc68hc(7)05h12 ? rev. 1.0 2 motorola motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. ?motorola, inc., 1997
mc68hc(7)05h12 ? rev. 1.0 general release specification motorola list of sections 1 non-disclosure agreement required general release specification ?mc68hc(7)05h12 list of sections list of sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 cpu and instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . 37 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 core timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 16-bit timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . 115 serial communications interface (sci). . . . . . . . . . . . 125 analog to digital converter . . . . . . . . . . . . . . . . . . . . . 143 eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
non-disclosure agreement required list of sections general release specification mc68hc(7)05h12 ? rev. 1.0 2 list of sections motorola pulse width modulator (pwm) . . . . . . . . . . . . . . . . . . . 159 eprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 173 mechanical specifications. . . . . . . . . . . . . . . . . . . . . . 183 index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
mc68hc(7)05h12 ? rev. 1.0 general release specification motorola table of contents 3 non-disclosure agreement required general release specification ?mc68hc(7)05h12 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.1 vdd and vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.2 avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.3 osc1, osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.5 irq /vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.6 pa0?a7/keyboard interrupt . . . . . . . . . . . . . . . . . . . . . . . 22 1.6.7 pb0?b7/eclk, miso, mosi, sck. . . . . . . . . . . . . . . . . . 22 1.6.8 pc0?c7/tcap0?, tcmp0?, rdi, tdo . . . . . . . . . . . . 22 1.6.9 pd0?d3/an0?n3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.10 vrefh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.11 pe0?e7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.12 pf0?f3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.13 pvdd1, pvss1, pvdd2, pvss2 . . . . . . . . . . . . . . . . . . . . 23 section 2. memory 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.1 system control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.5 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
non-disclosure agreement required table of contents general release specification mc68hc(7)05h12 ? rev. 1.0 4 table of contents motorola 2.6 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.7 user eprom (for the 705 version only) . . . . . . . . . . . . . . . . . . 35 2.8 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 section 3. cpu and instruction set 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.4 program counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 instruction set overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . 46 3.7.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . 47 3.7.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.7.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . 50 3.7.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 section 4. interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
table of contents mc68hc(7)05h12 ? rev. 1.0 general release specification motorola table of contents 5 non-disclosure agreement required 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.3 cpu interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.4 reset interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.5 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.6 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.7 external interrupt (irq/keyboard) . . . . . . . . . . . . . . . . . . . . . . 63 4.8 8-bit timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.9 16-bit timer1 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.10 16-bit timer2 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.11 sci interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.12 spi interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.13 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 section 5. resets 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3 external reset (reset ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.5 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6 computer operating properly reset (copr). . . . . . . . . . . . . . 70 5.6.1 resetting the cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6.2 cop during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6.3 cop watchdog timer considerations . . . . . . . . . . . . . . . . 71 5.6.4 cop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.7 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.8 low voltage reset (lvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.8.1 lvr operation in wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
non-disclosure agreement required table of contents general release specification mc68hc(7)05h12 ? rev. 1.0 6 table of contents motorola section 6. operating modes 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3 user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.5.2 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.5.3 slow mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 section 7. input/output ports 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.3.1 port a keyboard interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.3.2 port a interrupt edge register . . . . . . . . . . . . . . . . . . . . . . 81 7.3.3 port a interrupt control register . . . . . . . . . . . . . . . . . . . . . 81 7.3.4 port a interrupt status register . . . . . . . . . . . . . . . . . . . . . 82 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.7 port e and port f (power drivers) . . . . . . . . . . . . . . . . . . . . . . 83 7.7.1 power drivers for 360 air core driven instruments. . . . . . 85 7.7.2 h-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.7.3 power driver circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.7.4 short circuit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.7.5 port e and port f mismatch registers . . . . . . . . . . . . . . . . 89 7.7.6 driver states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.7.7 port e and port f configurations . . . . . . . . . . . . . . . . . . . . 92 7.7.8 h-bridge control with the pwm . . . . . . . . . . . . . . . . . . . . . 94 7.8 port e and port f during wait mode . . . . . . . . . . . . . . . . . . . 95 7.9 input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
table of contents mc68hc(7)05h12 ? rev. 1.0 general release specification motorola table of contents 7 non-disclosure agreement required section 8. core timer 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3.1 core timer status and control register (ctscr) . . . . . . . 99 8.3.2 computer operating properly (cop) watchdog reset. . . 101 8.3.3 core timer counter register (ctcr). . . . . . . . . . . . . . . . 101 8.4 core timer during wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 section 9. 16-bit timers 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.3.1 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.3.2 output compare registers . . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.3 output compare register 1 . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.4 output compare register 2 . . . . . . . . . . . . . . . . . . . . . . . 107 9.3.5 input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.6 input capture register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.7 input capture register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3.8 timer control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.3.9 timer control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.3.10 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.4 timer during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 section 10. serial peripheral interface (spi) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.3 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.3.1 master in slave out (miso) . . . . . . . . . . . . . . . . . . . . . . . 116 10.3.2 master out slave in (mosi) . . . . . . . . . . . . . . . . . . . . . . . 117 10.3.3 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.4 spi functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.5.1 spi control register (spcr) . . . . . . . . . . . . . . . . . . . . . . 121
non-disclosure agreement required table of contents general release specification mc68hc(7)05h12 ? rev. 1.0 8 table of contents motorola 10.5.2 spi status register (spsr) . . . . . . . . . . . . . . . . . . . . . . . 123 10.5.3 spi data i/o register (spdat) . . . . . . . . . . . . . . . . . . . . 124 10.6 spi during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 section 11. serial communications interface (sci) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.4 receiver wake-up operation . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.4.1 idle line wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.4.2 address mark wake-up. . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.5 receive data (rdi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.6 start bit detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.7 transmit data (tdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.8 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.8.1 serial communications data register (scdat). . . . . . . . 135 11.8.2 serial communications control register 1 (sccr1) . . . . 136 11.8.3 serial communications control register 2 (sccr2) . . . . 137 11.8.4 serial communications status register (scsr) . . . . . . . 138 11.8.5 baud rate register (baud) . . . . . . . . . . . . . . . . . . . . . . . 140 11.9 sci during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 section 12. analog to digital converter 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.3 a/d principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.4 a/d operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.5 internal and master oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 145 12.6 a/d registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.6.1 a/d status and control register (adscr) . . . . . . . . . . . . 146 12.6.2 a/d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.7 a/d during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.8 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
table of contents mc68hc(7)05h12 ? rev. 1.0 general release specification motorola table of contents 9 non-disclosure agreement required 12.9 conversion accuracy definitions . . . . . . . . . . . . . . . . . . . . . . 150 12.9.1 transfer curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.9.2 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.9.3 quantization error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.4 offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.5 gain scale error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.6 differential linearity error . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.7 integral linearity error. . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.8 total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 section 13. eeprom 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.3 eeprom control register (eepcr) . . . . . . . . . . . . . . . . . . . 154 13.4 eeprom options register (eeopr) . . . . . . . . . . . . . . . . . . 155 13.5 eeprom read, erase and programming procedures . . . . . 156 13.5.1 read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13.5.2 erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13.5.3 programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.6 operation in wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 section 14. pulse width modulator (pwm) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.3.1 pwm channel microshifting . . . . . . . . . . . . . . . . . . . . . . . 161 14.4 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.4.1 pwm data registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.4.2 pwm control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.4.3 pwm channel enable register. . . . . . . . . . . . . . . . . . . . . 165 14.4.4 pwm channel polarity register . . . . . . . . . . . . . . . . . . . . 165 14.5 pwm during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
non-disclosure agreement required table of contents general release specification mc68hc(7)05h12 ? rev. 1.0 10 table of contents motorola section 15. eprom 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.3 eprom bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.3.1 bootloader functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.4 eprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.4.1 eprom programming register (eprog) . . . . . . . . . . . . 170 15.5 mask option register (mor) . . . . . . . . . . . . . . . . . . . . . . . . . 171 section 16. electrical characteristics 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 16.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 16.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 16.4 power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 16.5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 176 16.6 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 16.7 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . 178 16.8 eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.9 eprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.10 power driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.11 power-on reset/low voltage reset characteristics . . . . . . . 181 section 17. mechanical specifications 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 17.2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 17.3 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 index
mc68hc(7)05h12 ? rev. 1.0 general release specification motorola list of figures 11 non-disclosure agreement required figure title page general release specification ?mc68hc(7)05h12 list of figures 1-1 mc68hc(7)05h12 block diagram . . . . . . . . . . . . . . . . . . . . 19 1-2 mc68hc(7)05h12 pin assignments (52-pin plcc package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2-1 mc68hc(7)05h12 memory map . . . . . . . . . . . . . . . . . . . . . 26 2-2 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2-3 i/o registers $0000?000f . . . . . . . . . . . . . . . . . . . . . . . . . 29 2-4 i/o registers $0010?001f . . . . . . . . . . . . . . . . . . . . . . . . . 30 2-5 i/o registers $0020?002f . . . . . . . . . . . . . . . . . . . . . . . . . 31 2-6 i/o registers $0030?003f . . . . . . . . . . . . . . . . . . . . . . . . . 32 2-7 i/o registers $0040?004f . . . . . . . . . . . . . . . . . . . . . . . . . 33 2-8 system control register (syscr). . . . . . . . . . . . . . . . . . . . 34 3-1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3-2 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3-3 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3-4 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3-5 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3-6 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4-1 interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . 62 5-1 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5-2 reset and por timing diagram . . . . . . . . . . . . . . . . . . . . 69 5-3 cop watchdog timer location register (copr) . . . . . . . . 72 5-4 low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6-1 wait flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7-1 port a interrupt edge register (paied) . . . . . . . . . . . . . . . . 81 7-2 port a interrupt control register (paicr) . . . . . . . . . . . . . . 81 7-3 port a interrupt status register (paisr) . . . . . . . . . . . . . . . 82 7-4 port e and port f (power drivers) . . . . . . . . . . . . . . . . . . . . 84 7-5 driving cross coupled coils . . . . . . . . . . . . . . . . . . . . . . . . 85
non-disclosure agreement required list of figures general release specification mc68hc(7)05h12 ? rev. 1.0 12 list of figures motorola 7-6 h-bridge driver circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7-7 power driver circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7-8 short circuit detection circuitry . . . . . . . . . . . . . . . . . . . . . . 88 7-9 port e mismatch register (pemism) . . . . . . . . . . . . . . . . . . 89 7-10 port f mismatch register (pfmism) . . . . . . . . . . . . . . . . . . 90 7-11 h-bridge states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7-12 port e configuration for two 360 instruments . . . . . . . . . . . 92 7-13 port f configuration for four 90 instruments (version 1). . . 93 7-14 port f configuration for four 90 instruments (version 2). . . 93 7-15 h-bridge control with pwm . . . . . . . . . . . . . . . . . . . . . . . . . 94 7-16 correspondence between data and pwm values. . . . . . . . 95 7-17 port i/o circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8-1 core timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8-2 core timer status and control register (ctscr) . . . . . . . 99 8-3 core timer counter register (ctcr) . . . . . . . . . . . . . . . . 102 9-1 timer block diagram (timer1) . . . . . . . . . . . . . . . . . . . . . . 104 9-2 16-bit timer register addresses (timer1). . . . . . . . . . . . . 105 9-3 timer control register 1 (tcr1) . . . . . . . . . . . . . . . . . . . . 110 9-4 timer control register 2 (tcr2) . . . . . . . . . . . . . . . . . . . . 112 9-5 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . 113 10-1 data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . 118 10-2 serial peripheral block diagram . . . . . . . . . . . . . . . . . . . . 119 10-3 serial peripheral interface master-slave interconnection . 120 10-4 spi control register (spcr) . . . . . . . . . . . . . . . . . . . . . . . 121 10-5 spi status register (spsr). . . . . . . . . . . . . . . . . . . . . . . . 123 10-6 spi data i/o register (spdat) . . . . . . . . . . . . . . . . . . . . . 124 11-1 serial communications interface block diagram . . . . . . . . 128 11-2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11-3 sampling technique used on all bits . . . . . . . . . . . . . . . . 132 11-4 examples of start bit sampling techniques . . . . . . . . . . . 133 11-5 sci artificial start following a framing error. . . . . . . . . . . 134 11-6 sci start bit following a break . . . . . . . . . . . . . . . . . . . . . 134 11-7 sci data register (scdat). . . . . . . . . . . . . . . . . . . . . . . . 135 11-8 sci control register 1 (sccr1) . . . . . . . . . . . . . . . . . . . . 136 11-9 sci control register 2 (sccr2) . . . . . . . . . . . . . . . . . . . . 137
list of figures mc68hc(7)05h12 ? rev. 1.0 general release specification motorola list of figures 13 non-disclosure agreement required 11-10 sci status register (scsr) . . . . . . . . . . . . . . . . . . . . . . . 138 11-11 sci baud rate register (baud) . . . . . . . . . . . . . . . . . . . . 140 12-1 a/d status and control register (adscr) . . . . . . . . . . . . 146 12-2 a/d data register (addr). . . . . . . . . . . . . . . . . . . . . . . . . 148 12-3 electrical model of an a/d input pin. . . . . . . . . . . . . . . . . . 149 12-4 transfer curve of an ideal 8-bit a/d converter . . . . . . . . . 150 13-1 eeprom control register (eepcr) . . . . . . . . . . . . . . . . . 154 13-2 eeprom options register (eeopr) . . . . . . . . . . . . . . . . 155 14-1 pwm block diagram (one channel) . . . . . . . . . . . . . . . . . . 160 14-2 pwm microshifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14-3 pwm data registers (pwm0?) . . . . . . . . . . . . . . . . . . . . 163 14-4 pwm control register (pwmctl). . . . . . . . . . . . . . . . . . . 164 14-5 pwm channel enable register (pwmen) . . . . . . . . . . . . 165 14-6 pwm channel polarity register (pwmpol) . . . . . . . . . . . 165 15-1 mc68hc705h12 programming circuit . . . . . . . . . . . . . . . 169 15-2 eprom programming register (eprog). . . . . . . . . . . . . 170 15-3 mask options registers (mor1 and mor2) . . . . . . . . . . . 171 17-1 52-pin plcc pin assignments. . . . . . . . . . . . . . . . . . . . . . 183 17-2 52-pin plcc package dimensions . . . . . . . . . . . . . . . . . . 184
non-disclosure agreement required list of figures general release specification mc68hc(7)05h12 ? rev. 1.0 14 list of figures motorola
mc68hc(7)05h12 ? rev. 1.0 general release specification motorola list of tables 15 non-disclosure agreement required table title page general release specification ?mc68hc(7)05h12 list of tables 3-1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . . . 46 3-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . . 47 3-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . . . 49 3-4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 50 3-5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3-7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4-1 reset/interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . 61 6-1 operating mode entry conditions . . . . . . . . . . . . . . . . . . . . . 75 7-1 i/o pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8-1 rti rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8-2 minimum cop reset times . . . . . . . . . . . . . . . . . . . . . . . . . 101 10-1 spi clock rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 11-1 first prescaler stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11-2 second prescaler stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12-1 a/d clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12-2 a/d channel assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13-1 erase mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14-1 pwm clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15-1 bootloader functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
non-disclosure agreement required list of tables general release specification mc68hc(7)05h12 ? rev. 1.0 16 list of tables motorola
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola general description 17 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.1 vdd and vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.2 avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.3 osc1, osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.5 irq/vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.6 pa0?a7/keyboard interrupt . . . . . . . . . . . . . . . . . . . . . . . 22 1.6.7 pb0?b7/eclk, miso, mosi, sck. . . . . . . . . . . . . . . . . . 22 1.6.8 pc0?c7/tcap0?, tcmp0?, rdi, tdo . . . . . . . . . . . . 22 1.6.9 pd0?d3/an0?n3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.10 vrefh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.11 pe0?e7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.12 pf0?f3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6.13 pvdd1, pvss1, pvdd2, pvss2 . . . . . . . . . . . . . . . . . . . . 23 1.2 introduction the mc68hc(7)05h12 hcmos microcomputer is a member of the m68hc05 family. this 8 bit microcomputer unit (mcu) contains on-chip oscillator, cpu, ram, (ep)rom, monitor rom, eeprom, parallel i/o, one core timer, cop watchdog system, two 16-bit programmable timers, synchronous and asynchronous serial interface, a 4 channel a/d converter, and an 8 channel 8-bit pwm with on-chip power driver circuitry.
non-disclosure agreement required general description general release speci?ation mc68hc(7)05h12 ? rev. 1.0 18 general description motorola 1.3 features hc05 core 52 plcc package 12032 bytes of user (ep)rom + 240 bytes of monitor rom + 16 bytes user vectors 256 bytes of ram 256 bytes of eeprom multipurpose core timer, real time interrupt (rti), cop watchdog timer two 16-bit timers with two input captures and two output compares each serial peripheral interface (spi) serial communications interface (sci) 4 channel a/d converter (8-bit resolution) keyboard interrupt for 8 i/o lines 8 channel 8-bit pwm system for control of h-bridge drivers 12 special power drivers to drive two major gauges and four minor gauges, with short circuit detection and slew rate limitation for reduced rfi (emc) power saving wait mode 2 selectable bus frequencies (slow mode) low voltage reset (lvr) circuitry to hold the cpu in reset
general description features mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola general description 19 non-disclosure agreement required figure 1-1. mc68hc(7)05h12 block diagram 0 000000011 cpu control arithmetic/logic unit accumulator index register stack pointer 0 0 program counter m68hc05 mcu reset condition code register 111hi ncz ddr a port a pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 core timer, internal oscillator divide by 2 or 8 16-bit irq v dd avdd osc1 osc2 user ram ?256 bytes reset 1 data direction register b port b pb7/ sck pb6/ mosi pb5/ miso pb4 pb3 pb2/eclk pb1 pb0 data direction register c port c user eeprom ?256 bytes pc7/ tdo pc6/ rdi pc5/tcmp1 pc4/tcmp0 pc3/tcap3 pc2/tcap2 pc1/tcap1 pc0/tcap0 timer1 cop cpu clock power monitor rom ?240 bytes pwm system port e pf3? port f pe7? key interrupt mask register 2 x pv dd 2 x pv ss sci spi 8-bit a/d converter user (ep)rom ?12032 bytes user vectors ?6 bytes port d pd3?/ an3? vrefh package: 52plcc v ss 16-bit timer2
non-disclosure agreement required general description general release speci?ation mc68hc(7)05h12 ? rev. 1.0 20 general description motorola 1.4 mask options there are three mask options: cop watchdog timer (enable/disable) low voltage reset (lvr) (enable/disable) ports e/f in wait mode (enable/disable) 1.5 pin assignments figure 1-2 shows the plcc pin assignments. figure 1-2. mc68hc(7)05h12 pin assignments (52-pin plcc package) 40 46 8 14 21 27 7 1 47 34 20 33 vrefh avdd vdd pc0/tcap0 pc1/tcap1 pc2/tcap2 pc3/tcap3 pc4/tcmp0 pc5/tcmp1 pc6/rdi pc7/tdo pvdd2 pvss2 pe7 pe6 pe5 pe4 pf3 pf2 pf1 pf0 pe3 pe2 pe1 pe0 pvss1 pb3 pb2/eclk pb1 pb0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pvdd1 pd3/an3 pd2/an2 pd1/an1 pd0/an0 vss reset osc1 osc2 irq /vpp pb7/sck pb6/mosi pb5/miso pb4
general description functional pin description mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola general description 21 non-disclosure agreement required 1.6 functional pin description the following paragraphs give a description of the general function of each pin. 1.6.1 vdd and vss power is supplied to the mcu through vdd and vss. vdd is the positive supply, and vss is ground. 1.6.2 avdd avdd is a separate supply pin providing power to the a/d converter. 1.6.3 osc1, osc2 the osc1 and osc2 pins are the connections for the on-chip oscillator. a crystal connected across these pins or an external signal connected to osc1 provides the oscillator clock. the frequency, f osc , of the oscillator or external clock source is divided by two or eight (slow mode) to produce the internal operating frequency, f op . 1.6.4 reset this pin can be used as an input to reset the mcu to a known start-up state by pulling it to the low state. the reset pin contains an internal schmitt trigger to improve its noise immunity as an input. the reset pin has an internal pulldown device that pulls the reset pin low when there is an internal cop watchdog reset, power-on reset (por), illegal address reset, or an internal low voltage reset. refer to section 5 resets . the reset pin contains an internal pullup device. 1.6.5 irq /vpp the interrupt triggering sensitivity of this pin can be programmed as falling edge sensitive or falling edge and low level sensitive.the irq pin
non-disclosure agreement required general description general release speci?ation mc68hc(7)05h12 ? rev. 1.0 22 general description motorola contains an internal schmitt trigger as part of its input to improve noise immunity. see section 4 interrupts for more details on the interrupts. irq /vpp is also the eprom programming power pin. 1.6.6 pa0?a7/keyboard interrupt these eight i/o lines comprise port a. the state of any pin is software programmable and all port a lines are configured as inputs during power-on or reset. the eight i/o lines are shared with the keyboard interrupt function. see section 7 input/output ports for more details on the i/o ports. 1.6.7 pb0?b7/eclk, miso, mosi, sck these eight i/o lines comprise port b. the state of any pin is software programmable and all port b lines are configured as inputs during power-on or reset. see section 7 input/output ports for more details on the i/o ports. the port pins pb5?b7 are shared with the spi system (miso, mosi, sck). see section 10 serial peripheral interface (spi) for more details on the operation of the spi. pin pb2 is shared with the internal system clock eclk. see section 2.3.1 system control register . 1.6.8 pc0?c7/tcap0?, tcmp0?, rdi, tdo these eight i/o lines comprise port c. the state of any pin is software programmable and all port c lines are configured as inputs during power-on or reset. see section 7 input/output ports for more details on the i/o ports. the port pins pc0?c5 are shared with the 16-bit timer (tcap0?, tcmp0?). see section 9 16-bit timers for more details on the operation of the 16-bit timers. the port pins pc6 and pc7 are shared with the sci system (rdi and tdo). refer to section 11 serial communications interface (sci) .
general description functional pin description mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola general description 23 non-disclosure agreement required 1.6.9 pd0?d3/an0?n3 these four input only lines comprise port d. see section 7 input/output ports for more details on the i/o ports. when the a/d converter is active, one of the 4 input lines may be selected by the a/d multiplexer for conversion. see section 12 analog to digital converter for more details on the operation of the a/d subsystem. 1.6.10 vrefh this pin provides the positive reference voltage for the a/d converter. vss provides the negative reference voltage for the a/d converter. 1.6.11 pe0?e7 these eight output only lines comprise port e. see section 7 input/output ports for more details on the i/o ports. the eight lines are shared with four pwm h-bridge driver pairs. the outputs are formed by special power drivers. see section 14 pulse width modulator (pwm) for more details on the pwm subsystem. 1.6.12 pf0?f3 these four output only lines comprise port f. see section 7 input/output ports for more details on the i/o ports. the four lines are shared with four pwm channels. the outputs are formed by special power drivers. see section 14 pulse width modulator (pwm) for more details on the pwm subsystem. 1.6.13 pvdd1, pvss1, pvdd2, pvss2 power is supplied to the power drivers through pvdd and pvss. pvdd1 and pvss1 are the supply pins for pe0? and pf0? and pvdd2 and pvss2 are the supply pins for pe4? and pf2?. the vss pin and the pvss1 and pvss2 pins are connected internally.
non-disclosure agreement required general description general release speci?ation mc68hc(7)05h12 ? rev. 1.0 24 general description motorola
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola memory 25 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 2. memory 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.1 system control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.5 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.7 user eprom (for the 705 version only) . . . . . . . . . . . . . . . . . . 35 2.8 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2 introduction the mc68hc(7)05h12 has a 16k byte memory map consisting of registers (for i/o, control and status), user ram, user rom (or eprom), eeprom, monitor rom, and reset and interrupt vectors as shown in figure 2-1 .
non-disclosure agreement required memory general release speci?ation mc68hc(7)05h12 ? rev. 1.0 26 memory motorola 2.3 registers the i/o and control registers reside in locations $0000?004f. the overall organization of these registers is shown in figure 1-2 . the bit assignments for each register are shown in figure 2-3 , figure 2-4 , figure 2-5 , figure 2-6 , and figure 2-7 . $0000 i/o registers 80 bytes $004f $0050 user ram 256 bytes stack ram 64 bytes $00c0 $00ff $014f $0150 unused 688 bytes $03ff $0400 user eeprom 256 bytes $04ff $0500 unused 2816 bytes $0fff $1000 user rom 12032 bytes $3eff $3f00 monitor rom 240 bytes $3fef $3ff0 user vectors 16 bytes $3fff figure 2-1. mc68hc(7)05h12 memory map
memory registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola memory 27 non-disclosure agreement required addr register name $0000 port a data register $0001 port b data register $0002 port c data register $0003 port d data register $0004 port a data direction register $0005 port b data direction register $0006 port c data direction register $0007 port c control register $0008 core timer control/status (ctcsr) $0009 core timer counter (ctcr) $000a unused $000b unused $000c unused $000d port a interrupt edge $000e port a interrupt control $000f port a interrupt status $0010 pwm data 0 $0011 pwm data 1 $0012 pwm data 2 $0013 pwm data 3 $0014 pwm data 4 $0015 pwm data 5 $0016 pwm data 6 $0017 pwm data 7 $0018 pwm control/sign $0019 pwm channel enable $001a pwm channel polarity $001b unused $001c eeprom control $001d reserved for 705 version $001e unused $001f test $0020 timer1 capture 1 high $0021 timer1 capture 1 low $0022 timer1 compare 1 high $0023 timer1 compare 1 low $0024 timer1 capture 2 high $0025 timer1 capture 2 low $0026 timer1 compare 2 high figure 2-2. i/o register summary
non-disclosure agreement required memory general release speci?ation mc68hc(7)05h12 ? rev. 1.0 28 memory motorola $0027 timer1 compare 2 low $0028 timer1 counter high $0029 timer1 counter low $002a timer1 alternate counter high $002b timer1 alternate counter low $002c timer1 control 1 $002d timer1 control 2 $002e timer1 status $002f unused $0030 timer2 capture 1 high $0031 timer2 capture 1 low $0032 timer2 compare 1 high $0033 timer2 compare 1 low $0034 timer2 capture 2 high $0035 timer2 capture 2 low $0036 timer2 compare 2 high $0037 timer2 compare 2 low $0038 timer2 counter high $0039 timer2 counter low $003a timer2 alternate counter high $003b timer2 alternate counter low $003c timer2 control 1 $003d timer2 control 2 $003e timer2 status $003f unused $0040 port e data register $0041 port e mismatch register $0042 port f data register $0043 port f mismatch register $0044 spi control $0045 spi status $0046 spi data i/o $0047 sci scdat $0048 sci sccr1 $0049 sci sccr2 $004a sci scsr $004b sci baud $004c unused $004d system control register $004e a/d data $004f a/d status/ctl addr register name figure 2-2. i/o register summary
memory registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola memory 29 non-disclosure agreement required addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0000 port a data r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 w $0001 port b data r pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 w $0002 port c data r pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 w $0003 port d data r0000 pd3 pd2 pd1 pd0 w $0004 port a data direction r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w $0005 port b data direction r ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 w $0006 port c data direction r ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 w $0007 port c control r0 0 tcmp1 tcmp0 0000 w $0008 ctscr r tof rtif tofe rtie 00 rt1 rt0 w rtof rtif $0009 ctcr r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $000a unimplemented r w $000b unimplemented r w $000c unimplemented r w $000d paied r edge7 edge6 edge5 edge4 edge3 edge2 edge1 edge0 w $000e paicr r paie7 paie6 paie5 paie4 paie3 paie2 paie1 paie0 w $000f paisr r paif7 paif6 paif5 paif4 paif3 paif2 paif1 paif0 w figure 2-3. i/o registers $0000?000f
non-disclosure agreement required memory general release speci?ation mc68hc(7)05h12 ? rev. 1.0 30 memory motorola addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0010 pwm data 0 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0011 pwm data 1 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0012 pwm data 2 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0013 pwm data 3 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0014 pwm data 4 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0015 pwm data 5 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0016 pwm data 6 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0017 pwm data 7 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0018 pwmctl r0 pwmc3 pwmc2 pwmc1 sign3 sign2 sign1 sign0 w pwmrs $0019 pwmen r pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w $001a pwmpol r ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w $001b unimplemented r w $001c eepcr r000 eeosc er1 eer0 eelat eepgm w $001d reserved for 705 ver- sion r w $001e unimplemented r w $001f test r00000000 w ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? figure 2-4. i/o registers $0010?001f
memory registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola memory 31 non-disclosure agreement required addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0020 timer 1 input capture1 high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0021 timer 1 input capture1 low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0022 timer 1 output compare1 high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0023 timer 1 output compare1 low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0024 timer 1 input capture2 high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0025 timer 1 input capture2 low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0026 timer 1 output compare2 high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0027 timer 1 output compare2 low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0028 timer 1 counter high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0029 timer 1 counter low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $002a timer 1 alternate counter high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $002b timer 1 alternate counter low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $002c timer 1 control 1 r ici1e ici2e oci1e toie co1e iedg1 iedg2 olvl1 w $002d timer 1 control 2 r0 0 oc2ie 0 co2e 00 olvl2 w $002e timer 1 status r ic1f ic2f oc1f tof tcap1 tcap2 oc2f 0 w $002f unimplemented r w figure 2-5. i/o registers $0020?002f
non-disclosure agreement required memory general release speci?ation mc68hc(7)05h12 ? rev. 1.0 32 memory motorola addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0030 timer 2 input capture1 high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0031 timer 2 input capture1 low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0032 timer 2 output compare1 high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0033 timer 2 output compare1 low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0034 timer 2 input capture2 high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0035 timer 2 input capture2 low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0036 timer 2 output compare2 high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0037 timer 2 output compare2 low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0038 timer 2 counter high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0039 timer 2 counter low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $003a timer 2 alternate counter high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $003b timer 2 alternate counter low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $003c timer 2 control 1 r ici1e ici2e oci1e toie co1e iedg1 iedg2 olvl1 w $003d timer 2 control 2 r 0 0 oc2ie 0 co2e 0 0 olvl2 w $003e timer 2 status r ic1f ic2f oc1f tof tcap1 tcap2 oc2f 0 w $003f unimplemented r w figure 2-6. i/o registers $0030?003f
memory registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola memory 33 non-disclosure agreement required addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0040 port e data r pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 w $0041 port e mismatch r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0042 port f data r0000 pf3 pf2 pf1 pf0 w $0043 port f mismatch r0000 bit 3 bit 2 bit 1 bit 0 w $0044 spi control r spie spe dod mstr cpol cpha spr1 spr0 w $0045 spi status r spif wcol 000000 w $0046 spi data r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0047 sci data r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0048 sci control 1 rr8 t8 0 m wake 000 w $0049 sci control 2 r tie tcie rie ilie te re rwu sbk w $004a sci status r tdre tc rdrf idle or nf fe 0 w $004b sci baud r0 spp scp1 scp0 0 scr2 scr1 scr0 w tclr rckb $004c unimplemented r w $004d system control r000 sc irq 00 eclk w $004e a/d data r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $004f a/d status/control r coco adrc adon 0 ch3 ch2 ch1 ch0 w figure 2-7. i/o registers $0040?004f
non-disclosure agreement required memory general release speci?ation mc68hc(7)05h12 ? rev. 1.0 34 memory motorola 2.3.1 system control register the mc68hc(7)05h12 contains a system control register which is located at $004d. this register is used to control the irq interrupt sensitivity, the bus frequency, and the external availability of the internal bus clock. sc ?system clock option after power on reset the internal bus frequency f op is = f osc /2. the sc bit allows the user to reduce the system speed to f osc /8. 1 = f op = f osc /8 (slow mode) 0 = f op = f osc /2 irq ?irq sensitivity irq edge or level sensitive 1 = irq input edge and level sensitive 0 = irq input edge sensitive eclk ?internal system clock available the eclk bit makes the internal system clock (bus frequency f op ) available to the user. refer to section 7.4 port b for more details. 1 = the pb2/eclk pin provides the internal system clock independently of the value of the port b data direction register 0 = the internal system clock is not available, the pb2/eclk pin is an ordinary i/o port line $004d bit 7 654321 bit 0 read: 0 0 0 sc irq 00 eclk write: reset: 00000000 figure 2-8. system control register (syscr)
memory ram mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola memory 35 non-disclosure agreement required 2.4 ram the user ram consists of 256 bytes ranging from $0050 to $014f. the stack begins at address $00ff. the stack pointer can access 64 bytes of ram in the range $00ff to $00c0. the stack is located in the middle of the ram address space. data written to addresses within the stack address range could be overwritten during stack activity. 2.5 rom the 12032 bytes of the user rom are located from $1000 to $3eff, plus 16 bytes of user vectors from $3ff0 to $3fff. 2.6 monitor rom the monitor rom ranges from $3f00 to $3fef. the vectors for the bootloader are located from $3fe0 to $3fef. 2.7 user eprom (for the 705 version only) the 12032 bytes of the user eprom are located from $1000 to $3efd, including two bytes of mask option registers (mor) at $3efe and $3eff, plus 16 bytes of user vectors from $3ff0 to $3fff. refer to section 15 eprom for programming details. 2.8 eeprom this device contains 256 bytes of eeprom. programming the eeprom is performed by the user on a single-byte basis by manipulating the eeprom control register, located at address $001c. refer to section 13 eeprom for programming details.
non-disclosure agreement required memory general release speci?ation mc68hc(7)05h12 ? rev. 1.0 36 memory motorola
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola cpu and instruction set 37 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 3. cpu and instruction set 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.4 program counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 instruction set overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.6.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . 46 3.7.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . 47 3.7.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.7.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . 50 3.7.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
non-disclosure agreement required cpu and instruction set general release speci?ation mc68hc(7)05h12 ? rev. 1.0 38 cpu and instruction set motorola 3.2 introduction this chapter describes the cpu registers and the hc05 instruction set. 3.3 cpu registers figure 3-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 3-1. programming model accumulator (a) a index register (x) x sp 1 1 0 0 0 0 0 00 0 pcl pch z c i n 1 h 1 1 0 4 75 condition code register (ccr) program counter (pc) stack pointer (sp) 0 7 8 15 15 5 7 7 0 0 0 half-carry flag interrupt mask negative flag zero flag carry/borrow flag 10 6
cpu and instruction set cpu registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola cpu and instruction set 39 non-disclosure agreement required 3.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and results of arithmetic and non- arithmetic operations. 3.3.2 index register in the indexed addressing modes, the cpu uses the byte in the index register to determine the conditional address of the operand. the 8-bit index register can also serve as a temporary data storage location. 3.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset or after the reset stack pointer (rsp) instruction, the stack pointer is preset to $00ff. the address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. bit 7 654321 bit 0 reset: unaffected by reset figure 3-2. accumulator bit 7 654321 bit 0 reset: unaffected by reset figure 3-3. index register bit 15 14 13 12 11 10 987654321 bit 0 0000000011 reset 0000000011111111 figure 3-4. stack pointer
non-disclosure agreement required cpu and instruction set general release speci?ation mc68hc(7)05h12 ? rev. 1.0 40 cpu and instruction set motorola the ten most significant bits of the stack pointer are permanently fixed at 000000011, so the stack pointer produces addresses from $00c0 to $00ff. if subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00ff and begins writing over the previously stored data. a subroutine uses two stack locations. an interrupt uses five locations. 3.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. the two most significant bits of the program counter are ignored internally. normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.3.5 condition code register the condition code register is an 8-bit register whose three most significant bits are permanently fixed at 111. the condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. the following paragraphs describe the functions of the condition code register. bit 15 14 13 12 11 10 987654321 bit 0 reset loaded with vector from $3ffe and $3fff figure 3-5. program counter bit 7 654321 bit 0 111hincz reset 1 1 1u1uuu figure 3-6. condition code register
cpu and instruction set cpu registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola cpu and instruction set 41 non-disclosure agreement required half-carry flag the cpu sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an add or adc operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. interrupt mask setting the interrupt mask disables interrupts. if an interrupt request occurs while the interrupt mask is logic zero, the cpu saves the cpu registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. normally, the cpu processes the latched interrupt as soon as the interrupt mask is cleared again. a return from interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its cleared state. after any reset, the interrupt mask is set and can be cleared only by a software instruction. negative flag the cpu sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. zero flag the cpu sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow flag.
non-disclosure agreement required cpu and instruction set general release speci?ation mc68hc(7)05h12 ? rev. 1.0 42 cpu and instruction set motorola 3.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logical operations defined by the instruction set. the binary arithmetic circuits decode instructions and set up the alu for the selected operation. most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the alu. the multiply instruction (mul) requires 11 internal clock cycles to complete this chain of operations. 3.5 instruction set overview the mcu instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. 3.6 addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: inherent immediate direct extended indexed, no offset indexed, 8-bit offset
cpu and instruction set addressing modes mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola cpu and instruction set 43 non-disclosure agreement required indexed, 16-bit offset relative 3.6.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 3.6.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. 3.6.3 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 3.6.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction.
non-disclosure agreement required cpu and instruction set general release speci?ation mc68hc(7)05h12 ? rev. 1.0 44 cpu and instruction set motorola 3.6.5 indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000?00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 3.6.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000?01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 3.6.7 indexed,16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing.
cpu and instruction set instruction types mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola cpu and instruction set 45 non-disclosure agreement required 3.6.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two? complement byte that gives a branching range of ?28 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 3.7 instruction types the mcu instructions fall into the following five categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions
non-disclosure agreement required cpu and instruction set general release speci?ation mc68hc(7)05h12 ? rev. 1.0 46 cpu and instruction set motorola 3.7.1 register/memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 3-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub
cpu and instruction set instruction types mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola cpu and instruction set 47 non-disclosure agreement required 3.7.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write operations on write-only registers. 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. 2. tst is an exception to the read-modify-write sequence be- cause it does not write a replacement value. table 3-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) bit set bset (1) clear register clr complement (ones complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (twos complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2)
non-disclosure agreement required cpu and instruction set general release speci?ation mc68hc(7)05h12 ? rev. 1.0 48 cpu and instruction set motorola 3.7.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ?28 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register.
cpu and instruction set instruction types mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola cpu and instruction set 49 non-disclosure agreement required table 3-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr
non-disclosure agreement required cpu and instruction set general release speci?ation mc68hc(7)05h12 ? rev. 1.0 50 cpu and instruction set motorola 3.7.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. table 3-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset
cpu and instruction set instruction types mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola cpu and instruction set 51 non-disclosure agreement required 3.7.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 3-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait
non-disclosure agreement required cpu and instruction set general release speci?ation mc68hc(7)05h12 ? rev. 1.0 52 cpu and instruction set motorola 3.8 instruction set summary table 3-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles h i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 c b0 b7 0 b0 b7 c
cpu and instruction set instruction set summary mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola cpu and instruction set 53 non-disclosure agreement required bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 table 3-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc
non-disclosure agreement required cpu and instruction set general release speci?ation mc68hc(7)05h12 ? rev. 1.0 54 cpu and instruction set motorola clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ?(m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (ones complement) m ? (m ) = $ff ?(m) a ? (a ) = $ff ?(a) x ? (x ) = $ff ?(x) m ? (m ) = $ff ?(m) m ? (m ) = $ff ?(m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ?(m) imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) ?1 a ? (a) ?1 x ? (x) ?1 m ? (m) ?1 m ? (m) ?1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 table 3-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc
cpu and instruction set instruction set summary mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola cpu and instruction set 55 non-disclosure agreement required jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) ?1 push (pch); sp ? (sp) ?1 pc ? effective address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (twos complement) m ? ?m) = $00 ?(m) a ? ?a) = $00 ?(a) x ? ?x) = $00 ?(x) m ? ?m) = $00 ?(m) m ? ?m) = $00 ?(m) dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 table 3-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc c b0 b7 0 b0 b7 c 0 c b0 b7
non-disclosure agreement required cpu and instruction set general release speci?ation mc68hc(7)05h12 ? rev. 1.0 56 cpu and instruction set motorola ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) ?(m) ?(c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) ?(m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1; push (x) sp ? (sp) ?1; push (a) sp ? (sp) ?1; push (ccr) sp ? (sp) ?1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 table 3-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc b0 b7 c
cpu and instruction set instruction set summary mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola cpu and instruction set 57 non-disclosure agreement required tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ?$00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts 0 inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow ?g pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry ?g z zero ?g hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ) negation (twos complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative ?g set or cleared n any bit not affected table 3-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc
non-disclosure agreement required cpu and instruction set general release speci?ation mc68hc(7)05h12 ? rev. 1.0 58 cpu and instruction set motorola table 3-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789 abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 ta x 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherentrel = relative imm = immediateix = indexed, no offset dir = directix1 = indexed, 8-bit offset ext = extendedix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola interrupts 59 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 4. interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.3 cpu interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.4 reset interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.5 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.6 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.7 external interrupt (irq/keyboard) . . . . . . . . . . . . . . . . . . . . . . 63 4.8 8-bit timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.9 16-bit timer1 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.10 16-bit timer2 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.11 sci interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.12 spi interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.13 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
non-disclosure agreement required interrupts general release speci?ation mc68hc(7)05h12 ? rev. 1.0 60 interrupts motorola 4.2 introduction the mcu can be interrupted eight different ways: 1. nonmaskable software interrupt instruction (swi) 2. external asynchronous interrupt (irq) 3. external keyboard wakeup on port a 4. internal 8 bit timer interrupt (ctimer) 5. internal 16-bit timer1 interrupt (timer1) 6. internal 16-bit timer2 interrupt (timer2) 7. internal serial communications interface interrupt (sci) 8. internal serial peripheral interface interrupt (spi) 4.3 cpu interrupt processing interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. if interrupts are not masked (i-bit in the ccr is clear) and the corresponding interrupt enable bit is set, then the processor will proceed with interrupt processing. otherwise, the next instruction is fetched and executed. if an interrupt occurs the processor completes the current instruction, then stacks the current cpu register states, sets the i-bit to inhibit further interrupts, and finally checks the pending hardware interrupts. if more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in table 4-1 will be serviced first. the swi is executed the same as any other instruction, regardless of the i-bit state. when an interrupt is to be processed the cpu fetches the address of the appropriate interrupt software service routine from the vector table at locations $3ff0 to $3fff as defined in table 4-1 .
interrupts cpu interrupt processing mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola interrupts 61 non-disclosure agreement required the m68hc05 cpu does not support interruptible instructions, therefore, the maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead. latency = (longest instruction execution time + 10) x t cyc secs an rti instruction is used to signify when the interrupt software service routine is completed. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. figure 4-1 shows the sequence of events that occur during interrupt processing. table 4-1. reset/interrupt vector addresses function source local mask global mask priority (1 = highest) vector address reset power-on logic none none 1 $3ffe?3fff reset pin cop watchdog software interrupt (swi) user code none none same priority as instruction $3ffc?3ffd external interrupt / irq pin none i bit 2 $3ffa?3ffb key wakeup pta key pins paie bits core timer interrupts rtif bit rtie bit i bit 3 $3ff8?3ff9 tof bit tofe bit 16-bit timer 1 interrupts icf bits icie bits i bit 4 $3ff6?3ff7 ocf bits ocie bits tof bit toie bit 16-bit timer 2 interrupts icf bits icie bits i bit 5 $3ff4?3ff5 ocf bits ocie bits tof bit toie bit spi interrupts spif bit spie i bit 6 $3ff2?3ff3 modf bit sci interrupts tdre bit tcie bit i bit 7 $3ff0?3ff1 tc bit rdrf bit rie bit or bit idle bit ilie bit
non-disclosure agreement required interrupts general release speci?ation mc68hc(7)05h12 ? rev. 1.0 62 interrupts motorola figure 4-1. interrupt processing flowchart y y y y y y y y from reset i-bit in ccr set? irq/key external interrupt clear irq request latch internal 8 bit core timer interrupt internal 16 bit timer1 interrupt internal 16 bit timer2 interrupt internal spi interrupt internal sci interrupt swi instruction ? rti instruction ? execute instruction restore registers from stack: ccr,a,x,pc set i bit in cc register load pc from appropriate vector fetch next instruction y stack pc,x,a,ccr n n n n n n n n n
interrupts reset interrupt sequence mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola interrupts 63 non-disclosure agreement required 4.4 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in figure 4-1 . a low level input on the reset pin or internally generated rst signal causes the program to vector to its starting address which is specified by the contents of memory locations $3ffe and $3fff. the i-bit in the condition code register is also set. the mcu is configured to a known state during this type of reset as described in section 5 resets . 4.5 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the i-bit in the ccr. if the i-bit is zero (interrupts enabled), the swi instruction executes after interrupts which were pending before the swi was fetched, or before interrupts generated after the swi was fetched. the interrupt service routine address is specified by the contents of memory locations $3ffc and $3ffd. 4.6 hardware interrupts all hardware interrupts except reset are maskable by the i-bit in the ccr. if the i-bit is set, all hardware interrupts (internal and external) are disabled. clearing the i-bit enables the hardware interrupts. there are two types of hardware interrupts (external, internal) which are explained in the following sections. 4.7 external interrupt (irq/keyboard) if the interrupt mask bit (i bit) of the ccr is set, all maskable interrupts (internal and external) are disabled. clearing the i bit enables interrupts. the interrupt request is latched immediately following the falling edge of irq. it is then synchronized internally and serviced by the interrupt service routine located at the address specified by the contents of $3ffa and $3ffb.
non-disclosure agreement required interrupts general release speci?ation mc68hc(7)05h12 ? rev. 1.0 64 interrupts motorola either a level-sensitive and edge-sensitive trigger, or an edge-sensitive- only trigger can be implemented by software. note: the internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the i bit is cleared. the bih and bil instructions will only apply to the level on the irq pin itself, and not to the output of the logic or function with the port a keyboard wakeup interrupts. the state of the individual port a pins can be checked by reading the appropriate port a pins as inputs. 4.8 8-bit timer interrupt this timer can create two types of interrupts. a timer overflow interrupt will occur whenever the 8-bit timer rolls over from $ff to $00 and the enable bit tofe is set. a real time interrupt will occur whenever the programmed time elapses and the enable bit rtie is set. this interrupt will vector to the interrupt service routine located at the address specified by the contents of memory location $3ff8 and $3ff9. 4.9 16-bit timer1 interrupt there are five different timer interrupt flags that cause a 16-bit timer1 interrupt whenever they are set and enabled. the interrupt flags are in the timer1 status register (tsr), and the enable bits are in the timer1 control register1 (tcr1). any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $3ff6 and $3ff7. 4.10 16-bit timer2 interrupt there are five different timer interrupt flags that cause a 16-bit timer2 interrupt whenever they are set and enabled. the interrupt flags are in the timer2 status register (tsr), and the enable bits are in the timer2 control register1 (tcr1). any of these interrupts will vector to the same
interrupts sci interrupt mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola interrupts 65 non-disclosure agreement required interrupt service routine, located at the address specified by the contents of memory location $3ff4 and $3ff5. 4.11 sci interrupt there are five different interrupt flags (tdre, tc, or, rdrf, idle) that will cause an sci interrupt whenever they are set and enabled. these five interrupt flags are found in the five most significant bits of the sci status register scsr. the actual processor interrupt is generated only if the i-bit in the condition code register is clear and the enable bit in the serial communications control register 2 (sccr2) is enabled. the sci interrupt causes the program counter to vector to the address pointed to by memory locations $3ff2?3ff3 which contain the start address of the interrupt service routine. software in the sci interrupt service routine must determine the priority and cause of the sci interrupt by examining the interrupt flags and the status bits in the serial communications status register (scsr). 4.12 spi interrupt there are two different spi interrupt flags that cause an spi interrupt whenever they are set and enabled. the interrupt flags are in the spi status register (spsr), and the enable bits are in the spi control register (spcr). either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3ff0 and $3ff1. 4.13 wait mode all modules that are capable of generating interrupts in wait mode will be allowed to do so if the module is configured properly. the i-bit is automatically cleared when wait mode is entered. interrupts detected on port a are recognized in wait modes.
non-disclosure agreement required interrupts general release speci?ation mc68hc(7)05h12 ? rev. 1.0 66 interrupts motorola
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola resets 67 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 5. resets 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3 external reset (reset). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.5 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6 computer operating properly reset (copr). . . . . . . . . . . . . . 70 5.6.1 resetting the cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6.2 cop during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6.3 cop watchdog timer considerations . . . . . . . . . . . . . . . . 71 5.6.4 cop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.7 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.8 low voltage reset (lvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.8.1 lvr operation in wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2 introduction the mcu can be reset from five sources: one external input and four internal restart conditions. the reset pin is an input with a schmitt trigger. all the internal peripheral modules will be reset by the internal reset signal (rst). refer to figure 5-2 for reset timing detail. the reset pin contains an internal pullup device. 5.3 external reset (reset ) the reset pin is the only external source of a reset. this pin is connected to a schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. this external reset occurs whenever the reset pin is pulled below the lower
non-disclosure agreement required resets general release speci?ation mc68hc(7)05h12 ? rev. 1.0 68 resets motorola threshold and remains in reset until the reset pin rises above the upper threshold. this active low input will generate the rst signal and reset the cpu and peripherals. when the reset pin goes high, the mcu will resume operation on the following cycle. note: activation of the rst signal is generally referred to as reset of the device, unless otherwise specified. the reset pin can also act as an open drain output. it will be pulled to a low state by an internal pulldown that is activated by any reset source. this reset pulldown device will be asserted for 3? cycles of the internal clock, f op , or as long as an internal reset source is asserted. when the external reset pin is asserted, the pulldown device will be turned on for the 3? internal clock cycles. 5.4 internal resets the four internally generated resets are the initial power-on reset function, the cop watchdog timer reset, the illegal address detector, and the low voltage reset. all internal resets will also assert (pull to logic zero) the external reset pin for the duration of the reset or 3? internal clock cycles, whichever is longer. figure 5-1. internal resets internal resets reset pin vdd internal reset logic internal pullup
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola resets 69 resets internal resets non-disclosure agreement required figure 5-2. reset and por timing diagram pch pcl osc1 2 reset internal address bus 1 3ffe 3fff v dd 4064 t cyc t cyc t rl internal data bus 1 3ffe 3ffe 3ffe 3ffe new pc 3fff notes: 1. internal timing signal and bus information not available externally. 2. osc1 line is not meant to represent frequency. it is only used to represent time. 3. the next rising edge of the internal processor clock following the rising edge of reset initiates the reset sequence. 4. v dd must fall to a level lower than v por in order to recognized as a power on reset. if lvr is enabled, vdd must fall below the lvr power off reset voltage vroff. 3 new new op code pcl pch new pc new pc op code new pc 0v por threshold (typ. 1-2v) 4 internal processor clock 1
non-disclosure agreement required resets general release speci?ation mc68hc(7)05h12 ? rev. 1.0 70 resets motorola 5.5 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabilize. the por is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilization delay of 4064 internal processor bus clock cycles after the oscillator becomes active. the por will generate the rst signal which will reset the cpu. if any other reset function is active at the end of this 4064 cycle delay, the rst signal will remain in the reset condition until the other reset condition(s) end. por will activate the reset pin pulldown device connected to the pin. v dd must drop below v por in order for the internal por circuit to detect the next rise of v dd . 5.6 computer operating properly reset (copr) the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. if the cop watchdog timer is allowed to time-out, an internal reset is generated to reset the mcu. regardless of an internal or external reset, the mcu comes out of a cop reset according to the pin conditions that determine mode selection. the cop reset function is enabled or disabled by the mask option (cop) and is verified during production testing. the cop watchdog reset will activate the internal pulldown device connected to the reset pin. 5.6.1 resetting the cop preventing a cop reset is done by writing a ??to the copr bit. this action will reset the counter and begin the time-out period again. the copr bit is bit 0 of address $3ff0. a read of address $3ff0 will return user data programmed at that location.
resets computer operating properly reset (copr) mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola resets 71 non-disclosure agreement required 5.6.2 cop during wait mode the cop will continue to operate normally during wait mode. the system should be configured to pull the device out of wait mode periodically and reset the cop by writing to the copr bit to prevent a cop reset. 5.6.3 cop watchdog timer considerations the cop watchdog timer is active in user mode if enabled by the mask option (cop). if the cop watchdog timer is selected, the cop will reset the mcu when it times out. therefore, it is recommended that the cop watchdog should be disabled for a system that must have intentional uses of the wait mode for periods longer than the cop time-out period.
non-disclosure agreement required resets general release speci?ation mc68hc(7)05h12 ? rev. 1.0 72 resets motorola 5.6.4 cop register the cop register is shared with the msb of a user interrupt vector as shown in figure 5-3 . reading this location will return whatever user data has been programmed at this location. writing a ??to the copr bit in this location will clear the cop watchdog timer. 5.7 illegal address reset an illegal address reset is generated when the cpu attempts to fetch an instruction from either unimplemented address space ($0150 to $03ff, $0500 to $0fff), monitor rom ($3f00 to $3fef) or i/o address space ($0000 to $004f). the illegal address reset will activate the internal pulldown device connected to the reset pin. note: no rts, rti or jmp,x instruction should be placed at the end of a memory block (ram $014f, eeprom $04ff, user rom $3eff) since this results in an illegal address reset. 5.8 low voltage reset (lvr) the internal low voltage (lvr) reset is generated when v dd falls below the lvr threshold v roff and will be release following a por delay starting when v dd rises above v ron . the lvr threshold is tested to be above the minimum operating voltage of the microcontroller and is intended to assure that the cpu will be held in reset when the v dd supply voltage is below reasonable operating limits. a mask option is $3ff0 bit 7 654321 bit 0 read: write: copr reset: figure 5-3. cop watchdog timer location register (copr)
resets low voltage reset (lvr) mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola resets 73 non-disclosure agreement required provided to disable the lvr when the device is expected to normally operate at low voltages. note that the v dd rise and fall slew rates must be within the specification for proper lvr operation. if the specification is not met, the circuit will operate properly following a delay of v dd /slew rate. the lvr will generate the rst signal which will reset the cpu and other peripherals. the low voltage reset will activate the internal pulldown device connected to the reset pin. if any other reset function is active at the end of the lvr reset signal, the rst signal will remain in the reset condition until the other reset condition(s) end. figure 5-4. low voltage reset note: an external capacity at the rst pin increases the reaction time for the generation of the internal reset and allows v dd drops. refer to figure 5-1 . 5.8.1 lvr operation in wait if enabled, the lvr supply voltage sense option is active during wait. any reset source can bring the mcu out of wait mode. vron vroff vdd reset hysteresis
non-disclosure agreement required resets general release speci?ation mc68hc(7)05h12 ? rev. 1.0 74 resets motorola
operating modes contents mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola operating modes 75 non-disclosure agreement required 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3 user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.5.2 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.5.3 slow mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.2 introduction the normal operating mode of the mc68hc(7)05h12 is user (or single chip) mode. there is also a monitor (or bootloader) mode, primarily for programming and evaluation purpose. in addition to these modes, there are three low power modes which may be entered and exited at will from user mode: wait, data retention and slow mode. table 6-1 shows the conditions required to enter the modes of operation on the rising edge of reset , were v tst = 2 x v dd . 6.3 user mode this is the intended mode of operation for executing user firmware. all user mode functions are explained in this specification. general release specification ?mc68hc(7)05h12 section 6. operating modes table 6-1. operating mode entry conditions irq pb0 mode v ss to v dd v ss to v dd user v tst v dd monitor
non-disclosure agreement required operating modes general release speci?ation mc68hc(7)05h12 ? rev. 1.0 76 operating modes motorola 6.4 monitor mode this mode is used for programming the on-chip eprom (705 version) and for the communication with a host computer via a standard rs-232 interface. 6.5 low power modes the mc68hc(7)05h12 is capable of running in one of several low- power operational modes. the wait instruction provides a mode that reduces the power required for the mcu by stopping various internal clocks. the flow of the wait mode is shown in figure 6-1 .
operating modes low power modes mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola operating modes 77 non-disclosure agreement required figure 6-1. wait flowchart 6.5.1 wait mode the wait instruction places the mcu in a low-power consumption mode. all cpu action is suspended, but the core timer, the 16 bit timers, the spi/sci, the adc, and the pwm will or can remain active. an y y y n n wait oscillator active timer clock active processor clocks stopped 16b timer, spi or sci interrupt keyboard interrupt, irq reset or lvr n y or ctimer. restart processor clock 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine
non-disclosure agreement required operating modes general release speci?ation mc68hc(7)05h12 ? rev. 1.0 78 operating modes motorola interrupt, if enabled, from the core timer or any peripheral still active in wait mode will cause the mcu to exit wait mode. during wait mode, the i bit in the ccr is cleared to enable interrupts. all other registers, memory, and input/output lines remain in their previous state. the core timer may be enabled to allow a periodic exit from the wait mode. 6.5.2 data retention mode the contents of ram and cpu registers are retained at data retention supply voltage v dr . this is called the data retention mode where the data is held, but the device is not guaranteed to operate. the reset pin must be held low during data-retention mode. to put the mcu into data retention mode: drive reset pin to zero. lower the v dd voltage. the reset pin must remain low continuously during data retention mode. to take the mcu out of data retention mode: return v dd to normal operating level. return the reset pin to logic one. 6.5.3 slow mode the slow mode function is controlled by the system clock option (sc bit) in the system control register. it allows the user to interconnect under software control an extra divide-by-4 between the oscillator and the internal clock driver. this feature allows all the internal operations to slow down and thus reduces power consumption. it is particularly useful when entering wait mode. see section 2.3.1 system control register .
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola input/output ports 79 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 7. input/output ports 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.3.1 port a keyboard interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.3.2 port a interrupt edge register . . . . . . . . . . . . . . . . . . . . . . 81 7.3.3 port a interrupt control register . . . . . . . . . . . . . . . . . . . . . 81 7.3.4 port a interrupt status register . . . . . . . . . . . . . . . . . . . . . 82 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.7 port e and port f (power drivers) . . . . . . . . . . . . . . . . . . . . . . 83 7.7.1 power drivers for 360 air core driven instruments . . . . . . 85 7.7.2 h-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.7.3 power driver circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.7.4 short circuit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.7.5 port e and port f mismatch registers . . . . . . . . . . . . . . . . 89 7.7.6 driver states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.7.7 port e and port f configurations . . . . . . . . . . . . . . . . . . . . 92 7.7.8 h-bridge control with the pwm . . . . . . . . . . . . . . . . . . . . . 94 7.8 port e and port f during wait mode . . . . . . . . . . . . . . . . . . . 95 7.9 input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.2 introduction in single chip mode there is a total of 40 lines arranged as three 8-bit i/o ports (ports a, b and c), one 4-bit input only port (port d), 12 output only lines arranged as one 8-bit (port e) and one 4-bit (port f) port. the i/o
non-disclosure agreement required input/output ports general release speci?ation mc68hc(7)05h12 ? rev. 1.0 80 input/output ports motorola ports are programmable as either inputs or outputs under software control of the data direction registers. note: to avoid a glitch on the output pins, write data to the i/o port data register before writing a one to the corresponding data direction register. 7.3 port a port a is an 8-bit bidirectional port. the port a data register is at $0000 and the port a data direction register (ddr) is at $0004. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 7.3.1 port a keyboard interrupt the keyboard interrupt consists of 8 individual edge-sensitive interrupts with 8 interrupt flags. the keyboard interrupt is generated by a logical or function of the 8 interrupt flags. the interrupt inputs are connected to pa0?. all interrupts are maskable. if the interrupt mask bit (i bit) in the condition code register is set, all interrupts are disabled. each interrupt can individually be masked by the corresponding paie7? bits in the port a interrupt control register. the trigger edges of the interrupt lines are programmable with the edg7? bits in the port a interrupt edge register. the pa0? input lines have no internal pull-up resistors.
input/output ports port a mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola input/output ports 81 non-disclosure agreement required 7.3.2 port a interrupt edge register edge7? ?port a interrupt edge these bits select the corresponding trigger edges of the interrupt lines pa7?a0. note that changing these bits can cause an interrupt, if the corresponding pin is ??and the bit changes from ??to ??or if the corresponding pin is ??and the bit changes from ??to ?? 1 = low to high edge sensitive 0 = high to low edge sensitive 7.3.3 port a interrupt control register paie7? ?port a interrupt enable each of these bits enables the corresponding port a pin as interrupt line 1 = corresponding port a interrupt enabled 0 = corresponding port a interrupt disabled $000d bit 7 654321 bit 0 read: edge7 edge6 edge5 edge4 edge3 edge2 edge1 edge0 write: reset: 00000000 figure 7-1. port a interrupt edge register (paied) $000e bit 7 654321 bit 0 read: paie7 paie6 paie5 paie4 paie3 paie2 paie1 paie0 write: reset: 00000000 figure 7-2. port a interrupt control register (paicr)
non-disclosure agreement required input/output ports general release speci?ation mc68hc(7)05h12 ? rev. 1.0 82 input/output ports motorola 7.3.4 port a interrupt status register paif7? ?port a interrupt flags these flags indicate which of the port a interrupt requests is pending. the 8 interrupt flags can be reset individually if a ??is written to the bit position. 1 = flag set when corresponding transition is sensed (even if interrupt is disabled), writing ??clears the flag 0 = no interrupt 7.4 port b port b is an 8-bit bidirectional port. the port b data register is at $0001, the port b data direction register (ddr) is at $0005. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. the port pins pb5?b7 are shared with the spi system (miso, mosi, sck). if the spi system is enabled the pins pb5?b7 are connected to the spi system. pin pb2 is shared with the internal system clock eclk. if the eclk bit in the system option register is set the internal system clock is available through pb2 independently of the value of the port b data direction register. refer to section 2.3.1 system control register for more information. when the eclk bit is set to ??the port b data direction register can still be read or written, but does not impact the eclk function at pin pb2. when the eclk bit is set to ??the port b data register bit 2 loses its contents and is not accessible. $000f bit 7 654321 bit 0 read: paif7 paif6 paif5 paif4 paif3 paif2 paif1 paif0 write: reset: 00000000 figure 7-3. port a interrupt status register (paisr)
input/output ports port c mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola input/output ports 83 non-disclosure agreement required 7.5 port c port c is an 8-bit bidirectional port. the port c data register is at $0002, the port c data direction register (ddr) is at $0006 and the port c control register is at $0007. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. reset clears the control register. the port pins pc0?c5 are shared with the 16-bit timers (tcap0?, tcmp0?). the lines pc0?c3 must be set to input by resetting the ddr to enable correct input capture function. if the tcmp1 or tcmp2 bit in the control register is set the pins pc5, pc4 function as output compare lines from the timer1 system otherwise they function as i/o lines. the port pins pc6, pc7 are shared with the sci system (rdi, tdo). if the sci is enabled the pins pc6, pc7 are connected to the sci system. 7.6 port d port d is an 4-bit input only port which shares all of its pins with the a/d converter (an0 through an3). the port d data register is located at address $0003. when the a/d converter is active, one of these 4 input lines may be selected by the a/d multiplexer for conversion. a logical read of a selected input port will always return 0. 7.7 port e and port f (power drivers) port e is an 8-bit output only port. the port e data register is at $0040. reset clears the data register. the eight lines are shared with four pwm h-bridge driver pairs (left and right). the outputs are formed by power drivers. the port e pwm lines can support two 360 (large angle) aircore instruments. port f is a 4-bit output only port. the port f data register is at $0042. reset clears the data register. the four lines are shared with four pwm channels. the outputs are formed by power drivers. the port f pwm lines can support four 90 (small angle) aircore instruments.
non-disclosure agreement required input/output ports general release speci?ation mc68hc(7)05h12 ? rev. 1.0 84 input/output ports motorola the power drivers have a separate voltage supply. pv dd 1 and pv ss 1 is the supply for pe0? and pf0? and pv dd 2 and pv ss 2 is the supply for pe4? and pf2?. the power drivers contain short circuit detection and slew rate limitation for reduced rfi (emc). figure 7-4. port e and port f (power drivers) pwm0 pwm1 pwm2 pwm3 left right left right left right left right pwm4 pf0 pf1 pwm5 pwm6 pwm7 pe4 pe5 pe6 pe7 pe0 pe1 pe2 pe3 pvdd1 pvdd2 pvss1 pvdd1 pvss2 pf2 pf3 pvdd2 pvss1 pvss2
input/output ports port e and port f (power drivers) mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola input/output ports 85 non-disclosure agreement required 7.7.1 power drivers for 360 air core driven instruments two pwm h-bridge systems are used to drive a system with cross coupled coils for a dashboard instrument. a single bridge is controlled by one pwm channel in combination with a further general purpose output (gpo) channel. it is capable of driving one of the two coils of an aircore instrument. the pulse width ratio in one of the two pwm channels corresponds to the average value of the current through the coil. figure 7-5. driving cross coupled coils the vector (i1,i2) of the currents through the coils in the cross coupled system is determined by the pulse widths (pw1, pw2). it also determines the elevation angle of the instrument. pwm1 pwm2 gpo1 gpo2 i2 i1 pw2 pw1 i1 i2
non-disclosure agreement required input/output ports general release speci?ation mc68hc(7)05h12 ? rev. 1.0 86 input/output ports motorola 7.7.2 h-bridge driver special power drivers in the h-bridge must be used to drive the system with coils, because high voltages at the driver outputs due to switching the coils would damage the circuits if the drivers are not protected against this. figure 7-6. h-bridge driver circuit in order to avoid large switching currents through the n- and pmos driver transistors both devices will not be active at the same time. on the other hand the switching delay between nmos and pmos transistor must be short, because the driver has to supply the coil circuit with a continuous current during the commutation. there would be diode currents into the bulk due to voltages below pv ss or greater then pv dd on the driver outputs if the commutation time is not short enough. low voltage drops on the driver transistors are also necessary to avoid these diode currents. pvdd pvss pwm gpo pout pout r l
input/output ports port e and port f (power drivers) mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola input/output ports 87 non-disclosure agreement required 7.7.3 power driver circuit figure 7-7. power driver circuit a high to low transition at the input vin causes a low to high transition at the gate of the pmos transistor. the nor-gate 3 blocks the transition at vin as long as the inverter 1 in the figure produces a low level. the result is that the pmos and the nmos devices are not active at the same time. an unsymmetrical sizing of the inverter 1 causes a fast propagation of the required low level to unblock the nor-gate. this results in a short switching delay. the inverter 2 in the figure realizes a fast low to high transition at the output pout. pvdd vin pou t pvss 1 3 pmos nmos 2
non-disclosure agreement required input/output ports general release speci?ation mc68hc(7)05h12 ? rev. 1.0 88 input/output ports motorola 7.7.4 short circuit detection the drivers contain a short circuit detection mechanism. the pin value of a single power driver output is compared with the set level of the actual power driver. a difference between both levels indicates a short circuit case at the actual power driver. the difference is stored as a logic ??in the corresponding bit of the mismatch registers of port e or port f. they can be polled by software. in the short circuit case precautions like shutting down the failed power driver can be taken. figure 7-8. short circuit detection circuitry figure 7-8 shows the circuitry for a single power driver port bit. each output bit of ports e and f can either be controlled directly by the data register or it is linked to the pwm function. the pwen signal which corresponds to the appropriate bit in the pwen register determines the functionality which will appear on the output. c hff mr dr pwen pwm db drr mrr mrw syn pout c d c d r q q q d vdd sout misl power driver exor
input/output ports port e and port f (power drivers) mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola input/output ports 89 non-disclosure agreement required the actual output level pout of a single power driver is compared with the set output level sout via the exor gate in the circuitry. the buffer c provides ?ow?if the ?igh?set output is significantly lower than pvdd or it provides a ?igh?if the ?ow?set output is significantly higher than pvss. the comparison result is latched with the appropriate signal syn which runs at bus frequency. the timing of the signal syn depends on the amount of microshifts for the actual pwm channel. the syn signal occurs 1/4 of a bus cycle later than the start of the pwm period. this ensures the pwm signal being stable on the output pout. a mismatch between the levels sout and pout which indicates a short circuit on the output results in a ?igh?signal latched by the hff. this latched mismatch signal misl is now stored in the corresponding bit mr of the mismatch register. the mismatch register of port e or port f can be polled in a proper time period like an interrupt flag register. a read ?igh? on the mismatch register bit has to be handled like an interrupt flag. it will be cleared by writing a logic ??back to this register. 7.7.5 port e and port f mismatch registers bit 7? ?port e short circuit indication the bits 7? indicate a short circuit on the port e. each bit is cleared by writing a ??to it. 1 = short circuit at the corresponding port e pin 0 = no short circuit at the corresponding port e pin $0041 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 00000000 figure 7-9. port e mismatch register (pemism)
non-disclosure agreement required input/output ports general release speci?ation mc68hc(7)05h12 ? rev. 1.0 90 input/output ports motorola bit 3? ?port f short circuit indication the bits 3? indicate a short circuit on the port f. each bit is cleared by writing a ??to it. 1 = short circuit at the corresponding port f pin 0 = no short circuit at the corresponding port f pin 7.7.6 driver states a single h-bridge realizes a current through the coil in both directions. three states are necessary to realize the required h-bridge operations for the 360 aircore instruments. forward state ?m1, m2 off; m0, m3 on backward state ?m0, m3 off; m1, m2 on off state ?m0, m2 off; m1, m3 on the mx are the driver transistors which form the h-bridge. the following circuits show how the bridge can operate in the different states. the driver transistors are drawn as switches for simplification. $0043 bit 7 654321 bit 0 read: 0000 bit 3 bit 2 bit 1 bit 0 write: reset: 00000000 figure 7-10. port f mismatch register (pfmism)
input/output ports port e and port f (power drivers) mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola input/output ports 91 non-disclosure agreement required figure 7-11. h-bridge states in each state the output driver gpo must hold the output p left or p right (left or right port line) at voltage pv dd ? drop while the pwm driver switches the opposite part of the h-bridge to ground. the pwm driver switches between forward state and off state or backward state and off state. the average current i is determined by the pulse width ratio at the pwm driver. current direction is changed by switching between forward and backward state. the output and the pwm functionality has also been changed between the two port lines when switching current direction. forward state off state backward state off state m1 m0 m1 m0 m1 m0 m1 m0 m3 m2 m3 m2 m3 m2 m3 m2 i i pwm gpo pwm gpo gpo pwm gpo pwm pppp pppp left right left left right left r l r l r l r l
non-disclosure agreement required input/output ports general release speci?ation mc68hc(7)05h12 ? rev. 1.0 92 input/output ports motorola 7.7.7 port e and port f configurations figure 7-12 shows a port e configuration which controls two 360 aircore instruments or stepper motors. one power driver block controls a single large angle instrument (360 ). this configuration ensures a minimum voltage drop mismatch between the two h-bridges of the block. note: one should not control a single instrument with h-bridges from different power driver blocks. the minimum voltage drop mismatch is only ensured within a single block. figure 7-12. port e configuration for two 360 instruments pwm0 pwm1 pwm2 pwm3 left right left right left right left right pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7
input/output ports port e and port f (power drivers) mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola input/output ports 93 non-disclosure agreement required figure 7-13. port f configuration for four 90 instruments (version 1) figure 7-14. port f configuration for four 90 instruments (version 2) figure 7-13 and figure 7-14 show two port f configuration with four 90 small angle instruments which are controlled by the pwm. the small angle instrument does not need a switching between two quadrants. it can be controlled by a single power driver and its pwm. note: if port e (pwm channels 0 to 3) is used to control small angle instruments, the sign bit in the pwm control register may not be changed during the operation with 90 instruments. this would exchange the functionality of pwm and gpo (general purpose output) between the left and the right port bit. pwm4 pf0 pf1 pwm5 pwm6 pwm7 pf2 pf3 pvss pvdd pwm4 pf0 pf1 pwm5 pwm6 pwm7 pf2 pf3 pvss pvdd
non-disclosure agreement required input/output ports general release speci?ation mc68hc(7)05h12 ? rev. 1.0 94 input/output ports motorola 7.7.8 h-bridge control with the pwm the current in the pwm can be adjusted in the range of ? max 256/256 and + i max 255/256. the current is a linear function of the 8+1bit 2? complement value in the data register of the pwm channel. the sign bit controls the current direction within the h-bridge. this will be done by exchanging the pwm and gpo functionality and inverting the pwm signal in the h-bridge when switching the sign-bit. figure 7-15. h-bridge control with pwm the following 3 bit pwm example in figure 7-16 shows the correspondence between the 2? complement values in the data register and the required pwm signal in the h-bridge. sign = 0 m1 m0 m3 m2 i pwm gpo = high p left right sign = 1 m1 m0 m3 m2 i gpo = high pwm pp left right pol = 1 r l r l
input/output ports port e and port f during wait mode mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola input/output ports 95 non-disclosure agreement required figure 7-16. correspondence between data and pwm values figure 7-16 shows that the pwm signal has to be inverted for the negative values in order to obtain the correct h-bridge signal which is drawn in figure 7-16 . (compare the periods for the values ? and 7). 7.8 port e and port f during wait mode in wait mode a mask option defines if port e and port f will be forced to output ?ow?or if port e and port f continue normal operation. 7.9 input/output programming bidirectional port lines may be programmed as an input or an output under software control. the direction of the pins is determined by the state of the corresponding bit in the port data direction register (ddr). each port has an associated ddr. any i/o port pin is configured as an output if its corresponding ddr bit is set to a logic one. a pin is configured as an input if its corresponding ddr bit is cleared to a logical zero. 7 : 2 1 0 ? ? : ? 0 111 0 010 0 001 0 000 1 111 1 110 1 000 sign
non-disclosure agreement required input/output ports general release speci?ation mc68hc(7)05h12 ? rev. 1.0 96 input/output ports motorola at power-on or reset, all ddrs are cleared, which configure all port pins as inputs. the data direction registers are capable of being written to or read by the processor. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. r/w is an internal signal. figure 7-17. port i/o circuitry note: if the i/o pin is an input and a read-modify (rmw) instruction is executed, the i/o pin will be read into the hc05 cpu and the computed result will then be written to the data latch. table 7-1. i/o pin functions r/w ddr i/o pin function 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in output mode. the output data latch is read. data direction register bit latched output data bit i/o pin input reg bit input i/o output internal hc05 connections
core timer contents mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola core timer 97 non-disclosure agreement required 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3.1 core timer status and control register (ctscr) . . . . . . . 99 8.3.2 computer operating properly (cop) watchdog reset. . . 101 8.3.3 core timer counter register (ctcr). . . . . . . . . . . . . . . . 101 8.4 core timer during wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.2 introduction the core timer for this device is a 15-stage multi-functional ripple counter. the features include timer over flow, power-on reset (por), real time interrupt (rti), and cop watchdog timer. general release specification ?mc68hc(7)05h12 section 8. core timer
non-disclosure agreement required core timer general release speci?ation mc68hc(7)05h12 ? rev. 1.0 98 core timer motorola figure 8-1. core timer block diagram as seen in figure 8-1 , the timer is driven by the output of the clock select circuit followed by a fixed divide by four prescaler. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the timer counter register (tcr) at address $09. a timer overflow function is implemented on the cop clear $9 ctcr 7-bit counter interrupt circuit $08 ctcsr rti select circuit overflow circuit detect cop watchdog timer ( ? 8) to reset logic to interrupt logic 8 8 f op f op /2 2 f op /2 10 por tcbp tcsr tcr internal processor clock tof rtif tofe rtie rt1 rt0 rrtif rtof timer control/status register timer counter register (tcr) ? 4 internal bus 8
core timer registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola core timer 99 non-disclosure agreement required last stage of this counter, giving a possible interrupt at the rate of f op /1024. two additional stages produce the por function at f op /4064. the timer counter bypass circuitry (available only in test mode) is at this point in the timer chain. this circuit is followed by two more stages, with the resulting clock (f op /16384) driving the real time interrupt circuit. the rti circuit consists of three divider stages with a 1 of 4 selector. the output of the rti circuit is further divided by eight to drive the mask optional cop watchdog timer circuit. the rti rate selector bits, and the rti and tof enable bits and flags are located in the timer control and status register at location $08. 8.3 registers 8.3.1 core timer status and control register (ctscr) the ctscr contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. figure 8-2 shows the value of each bit in the ctscr when coming out of reset. tof ?timer over flow tof is a read-only status bit and is set when the 8-bit ripple counter rolls over from $ff to $00. a cpu interrupt request will be generated if tofe is set. reset clears tof. rtif ?real time interrupt flag the real time interrupt circuit consists of a three stage divider and a 1 of 4 selector. the clock frequency that drives the rti circuit is f op /2 13 (or f op /8192) with three additional divider stages giving a maximum $0008 bit 7 654321 bit 0 read: tof rtif tofe rtie 00 rt! rt0 write: rtof rrtif reset: 00000011 figure 8-2. core timer status and control register (ctscr)
non-disclosure agreement required core timer general release speci?ation mc68hc(7)05h12 ? rev. 1.0 100 core timer motorola interrupt period of about 250ms seconds at a crystal frequency of 1 mhz. rtif is a read-only status bit and is set when the output of the chosen (1 of 4 selection) stage goes active. a cpu interrupt request will be generated if rtie is set. reset clears rtif. tofe ?timer over flow enable when this bit is set, a cpu interrupt request is generated when the tof bit is set. reset clears this bit. rtie ?real time interrupt enable when this bit is set, a cpu interrupt request is generated when the rtif bit is set. reset clears this bit. rtof ?reset timer overflow flag this bit reads always as ?? writing a ??to this bit clears the timer overflow flag (tof). writing a zero to this bit has no effect. rrtif ?reset real time interrupt flag this bit reads always a ?? writing a ??to this bit clears the real time interrupt flag (rtif). writing a zero to this bit has no effect. rt1, rt0 ?real time interrupt rate select these two bits select one of four taps from the real time interrupt circuit. figure 8-1 shows the available interrupt rates with several f op values. reset sets these rt0 and rt1, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. care should be taken when altering rt0 and rt1 if the time-out period is imminent or uncertain. if the selected tap is modified during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared before changing rti taps. table 8-1. rti rates rti rates at bus frequency f op specified: rt1:rt0 500 khz 1.000 mhz 2.000 mhz 2.4576 mhz ratio 00 32.768ms 16.384ms 8.192ms 6.667ms 2 14 /f op
core timer registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola core timer 101 non-disclosure agreement required 8.3.2 computer operating properly (cop) watchdog reset the cop watchdog timer function is implemented on this device by using the output of the rti circuit and further dividing it by eight. the minimum cop reset rates are listed in table 8-2 . if the cop circuit times out, an internal reset is generated and the normal reset vector is fetched. preventing a cop time-out is done by writing a ??to bit 0 of address $3ff0. when the cop is cleared, only the final divide by eight stage (output of the rti) is cleared. 8.3.3 core timer counter register (ctcr) the timer counter register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at f op divided by 4 and can be used for various functions including a software input capture. extended time periods can be attained using the tof function to increment a temporary ram storage location thereby simulating a 16-bit (or more) counter. 01 65.536ms 32.768ms 16.384ms 13.333ms 2 15 /f op 10 131.072ms 65.536ms 32.768ms 26.667ms 2 16 /f op 11 262.144ms 131.072ms 65.536ms 53.333ms 2 17 /f op table 8-1. rti rates rti rates at bus frequency f op specified: rt1:rt0 500 khz 1.000 mhz 2.000 mhz 2.4576 mhz ratio table 8-2. minimum cop reset times minimum cop reset bus frequency at f op specified: rt1:rt0 500 khz 1.000 mhz 2.000 mhz 2.4576 mhz ratio 00 229.376ms 114.689ms 57.344ms 46.666ms 7*2 14 /f op 01 458.752ms 229.376ms 114.689ms 93.333ms 7*2 15 /f op 10 917.504ms 458.752ms 229.376ms 186.666ms 7*2 16 /f op 11 1835.000ms 917.504ms 458.752ms 373.333ms 7*2 17 /f op
non-disclosure agreement required core timer general release speci?ation mc68hc(7)05h12 ? rev. 1.0 102 core timer motorola the power-on cycle clears the entire counter chain and begins clocking the counter. after 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. when reset is asserted anytime during operation (other than por), the counter chain will be cleared. 8.4 core timer during wait the cpu clock halts during the wait mode, but the core timer remains active. if the ctimer interrupts are enabled, then a ctimer interrupt will cause the processor to exit the wait mode. $0009 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 00000000 figure 8-3. core timer counter register (ctcr)
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola 16-bit timers 103 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 9. 16-bit timers 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.3.1 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.3.2 output compare registers . . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.3 output compare register 1 . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.4 output compare register 2 . . . . . . . . . . . . . . . . . . . . . . . 107 9.3.5 input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.6 input capture register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.7 input capture register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3.8 timer control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.3.9 timer control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.3.10 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.4 timer during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.2 introduction the mc68hc(7)05h12 has two 16-bit timers (timer1 and timer2) each with two channels. the output compare function in timer2 has no external outputs, so it is used for generating precision time intervals and interrupts only. write access to the corresponding output level register bits olvl3 and olvl4 has no effect. apart from this difference in the external connections, the internal operation of both is identical (each timer having its own set of registers, see section 2.3 registers ), therefore only a complete description of timer1 is given. the timer consists of a 16-bit, free running counter driven by a fixed divide-by-four prescaler. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from several
non-disclosure agreement required 16-bit timers general release speci?ation mc68hc(7)05h12 ? rev. 1.0 104 16-bit timers motorola microseconds to many seconds. refer to figure 9-1 for a timer block diagram. because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. these registers contain the high and low byte of that functional segment. generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. note: the i bit in the ccr should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur. figure 9-1. timer block diagram (timer1) input capture 1 register clock internal bus /4 internal processor 16-bit free running counter counter alternate register 8-bit buffer high byte low byte $2a $2b $28 $29 high byte low byte $24 $21 overflow detect circuit edge detect circuit timer status reg. ici2e iedg1 olvl1 output level (tcom p1) interrupt circuit toie oci1e edge input (tcap2) d clk c q ic1f ic2f oc1f tof input capture 2 register byte $25 $20 high edge detect circuit iedg2 ici1e oc2f output compare register 1 byte $26 $27 output compare circuit 1 output compare register 2 byte output compare circuit 2 oci2e olvl2 reset d clk c q output level (tcomp 0) tcr1($2c) tcr2($2d) high high low byte low byte low byte $22 $23 edge input (tcap1)
16-bit timers registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola 16-bit timers 105 non-disclosure agreement required 9.3 registers 9.3.1 counter the key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. the double-byte, free-running counter can be read from either of two locations, $28?29 (counter register) or $2a?2b (counter alternate register). a read from only the least significant byte (lsb) of the free- running counter ($29, $2b) receives the count value at the time of the read. if a read of the free-running counter or counter alternate register first addresses the most significant byte ($28, $2a), the lsb ($29, $2b) is transferred to a buffer. this buffer value remains fixed after the first msb read, even if the user reads the msb several times. this buffer is accessed when reading the free-running counter or counter alternate addr register name $0020 timer1 capture 1 high $0021 timer1 capture 1 low $0022 timer1 compare 1 high $0023 timer1 compare 1 low $0024 timer1 capture 2 high $0025 timer1 capture 2 low $0026 timer1 compare 2 high $0027 timer1 compare 2 low $0028 timer1 counter high $0029 timer1 counter low $002a timer1 alternate counter high $002b timer1 alternate counter low $002c timer1 control 1 $002d timer1 control 2 $002e timer1 status figure 9-2. 16-bit timer register addresses (timer1)
non-disclosure agreement required 16-bit timers general release speci?ation mc68hc(7)05h12 ? rev. 1.0 106 16-bit timers motorola register lsb ($29 or $2b) and thus completes a read sequence of the total counter value. in reading either the free-running counter or counter alternate register, if the msb is read, the lsb must also be read to complete the sequence. the counter alternate register differs from the counter register in one respect: a read of the counter register msb can clear the timer overflow flag (tof). therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the tof. 9.3.2 output compare registers there are two output compare registers: output compare register 1 and output compare register 2. output compare registers can be used for several purposes such as controlling an output waveform or indicating when a period of time has elapsed. all bits are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. 9.3.3 output compare register 1 the 16-bit output compare register 1 is made up of two 8-bit registers at locations $22 (msb) and $23 (lsb). the output compare register contents are compared with the contents of the free-running counter once every four internal processor clock cycles. if a match is found, the output compare flag oc1f (bit 5 of the timer status register ($2e)) is set and the corresponding output level olvl1 bit is clocked to tcmp1 output. the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (oci1e) is set. after a processor write cycle to the output compare register 1 containing the msb ($22), the output compare function is inhibited until the lsb
16-bit timers registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola 16-bit timers 107 non-disclosure agreement required ($23) is also written. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb ($23) will not inhibit the compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. the processor can write to either byte of the output compare register 1 without affecting the other byte. the output level (olvl1) bit is clocked to the output level register regardless of whether the output compare flag (oc1f) is set or clear. because the output compare flag oc1f and the output compare register 1 are undetermined at power-on and are not affected by external reset, care must be exercised when initializing the output compare function. the following procedure is recommended write the high byte to the compare register 1 to inhibit further compares until the low byte is written. reading the status register arms the oc1f if it is already set. write the output compare register 1 low byte to enable the output compare 1 function with the flag clear. the purpose of this procedure is to prevent the oc1f bit from being set between the time it is read and the write to the corresponding output compare register. 9.3.4 output compare register 2 the 16-bit output compare register 2 is made up of two 8-bit registers at locations $26 (msb) and $27 (lsb). the output compare register contents are compared with the contents of the free-running counter once every four internal processor clock cycles. if a match is found, the output compare flag oc2f (bit 1 of the timer status register ($2e)) is set and the corresponding output level olvl2 bit is clocked to tcmp2 output.
non-disclosure agreement required 16-bit timers general release speci?ation mc68hc(7)05h12 ? rev. 1.0 108 16-bit timers motorola the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (oci2e) is set. after a processor write cycle to the output compare register 2 containing the msb ($26), the output compare function is inhibited until the lsb ($27) is also written. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb ($27) will not inhibit the compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. the processor can write to either byte of the output compare register 2 without affecting the other byte. the output level (olvl2) bit is clocked to the output level register regardless of whether the output compare flag (oc2f) is set or clear. because the output compare flag oc2f and the output compare register 2 are undetermined at power-on, and are not affected by external reset care must be exercised when initializing the output compare function. a procedure as recommended for compare register 1 should be followed. 9.3.5 input capture registers there are two identical input capture registers: input capture register 1 and input capture register 2. the two following sections describe these two registers. 9.3.6 input capture register 1 two 8-bit registers, which make up the 16-bit input capture register 1, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition on the tcap1 pin. the level transition which triggers the counter transfer is defined by the corresponding input edge bit (iedg1). reset does not affect the contents of the input capture register.
16-bit timers registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola 16-bit timers 109 non-disclosure agreement required iedg1 ?capture on negative/positive edge 1 = capture on positive edge 0 = capture on negative edge an interrupt can also accompany a capture provided the corresponding interrupt enable bit, ici1e is set. the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (ic1f) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register most significant byte ($20), the counter transfer is inhibited until the least significant byte ($21) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($21) does not inhibit the free- running counter transfer since they occur on opposite edges of the internal bus clock. 9.3.7 input capture register 2 two 8-bit registers, which make up the 16-bit input capture register 2, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition on the tcap2 pin. the level transition which triggers the counter transfer is defined by the corresponding input edge bit (iedg2). reset does not affect the contents of the input capture register.
non-disclosure agreement required 16-bit timers general release speci?ation mc68hc(7)05h12 ? rev. 1.0 110 16-bit timers motorola iedg2 ?capture on negative/positive edge 1 = capture on positive edge 0 = capture on negative edge an interrupt can also accompany a capture provided the corresponding interrupt enable bit, ici2e is set. the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (ic2f) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register most significant byte ($24), the counter transfer is inhibited until the least significant byte ($25) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($25) does not inhibit the free- running counter transfer since they occur on opposite edges of the internal bus clock. 9.3.8 timer control register 1 $002c bit 7 654321 bit 0 read: ici1e ici2e oci1e toie co1e iedg1 iedg2 olvl1 write: reset: 00000uu0 figure 9-3. timer control register 1 (tcr1)
16-bit timers registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola 16-bit timers 111 non-disclosure agreement required ici1e ?input capture 1 interrupt enable 1 = interrupt enabled 0 = interrupt disabled ici2e ?input capture 2 interrupt enable 1 = interrupt enabled 0 = interrupt disabled oci1e ?output compare 1 interrupt enable 1 = interrupt enabled 0 = interrupt disabled toie ?timer overflow interrupt enable 1 = interrupt enabled 0 = interrupt disabled co1e ?timer compare 1 output enable reset clears this bit. 1 = output of timer compare 1is enabled 0 = output of timer compare 1is disabled, i.e. held low iedg1 ?input edge value of input edge determines which level transition on tcap1 pin will trigger free-running counter transfer to the input capture register 1. 1 = positive edge 0 = negative edge iedg2 ?input edge value of input edge determines which level transition on tcap2 pin will trigger free-running counter transfer to the input capture register 2. 1 = positive edge 0 = negative edge olvl1 ?output level 1 value of output level is clocked into output level register by the next successful output compare 1, and will appear on the tcmp1 pins. 1 = high output 0 = low output
non-disclosure agreement required 16-bit timers general release speci?ation mc68hc(7)05h12 ? rev. 1.0 112 16-bit timers motorola 9.3.9 timer control register 2 oci2e ?output compare 2 interrupt enable 1 = interrupt enabled 0 = interrupt disabled co2e ?timer compare 2 output enable reset clears this bit. 1 = output of timer compare 2 is enabled 0 = output of timer compare 2 is disabled, i.e. held low olvl2 ?output level 2 value of output level is clocked into output level register by the next successful output compare 2, and will appear on the tcmp2 pin. 1 = high output 0 = low output bits 1,2,4,6 & 7 of trc2 are no used and always read zero. note: only tcmp1 and tcmp2 of timer 1 are available at port c, timer 2 has no tcmp pins. $002d bit 7 654321 bit 0 read: 0 0 oci2e 0 co2e 00 olvl2 write: reset: u u 0 0 u 0 0 u figure 9-4. timer control register 2 (tcr2)
16-bit timers registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola 16-bit timers 113 non-disclosure agreement required 9.3.10 timer status register the timer status register is a read-only register containing timer status flags. ic1f ?input capture 1 flag 1 = flag set when selected polarity edge is sensed by input capture 1 edge detector 0 = flag cleared when tsr and input capture 1 register? low byte is accessed ic2f ?input capture 2 flag 1 = flag set when selected polarity edge is sensed by input capture 2 edge detector 0 = flag cleared when tsr and input capture 2 register? low byte is accessed oc1f ?output compare 1 flag 1 = flag set when output compare register 1 contents match the free-running counter contents 0 = flag cleared when tsr and output compare register 1 low byte are accessed tof ?timer overflow flag 1 = flag set when free-running counter transition from $ffff to $0000 occurs 0 = flag cleared when tsr and counter low register are accessed tcap1 ?timer capture 1 this bit reflects the current state of the timer capture 1 input. tcap2 ?timer capture 2 this bit reflects the current state of the timer capture 2 input. $002e bit 7 654321 bit 0 read: ic1f ic2f oc1f tof tcap1 tcap2 oc2f 0 write: reset: uuuu1 1u0 figure 9-5. timer status register (tsr)
non-disclosure agreement required 16-bit timers general release speci?ation mc68hc(7)05h12 ? rev. 1.0 114 16-bit timers motorola oc2f ?output compare 2 flag 1 = flag set when output compare register 2 contents match the free-running counter contents 0 = flag cleared when tsr and output compare register 2 low byte are accessed accessing the timer status registers satisfies the first condition required to clear status bits. the remaining step is to access the registers corresponding to the status bit. a problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. the timer status register is read or written when tof is set, and 2. the lsb of the free-running counter is read but not for the purpose of servicing the flag the counter alternate register contains the same value as the free- running counter; therefore this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. 9.4 timer during wait mode the cpu clock halts during the wait mode but the timer keeps on running. if a reset is used to exit the wait mode the counters are forced to $fffc. if interrupts are enabled a timer interrupt will cause the processor to exit wait mode.
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial peripheral interface (spi) 115 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 10. serial peripheral interface (spi) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.3 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.3.1 master in slave out (miso) . . . . . . . . . . . . . . . . . . . . . . . 116 10.3.2 master out slave in (mosi) . . . . . . . . . . . . . . . . . . . . . . . 117 10.3.3 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.4 spi functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.5.1 spi control register (spcr) . . . . . . . . . . . . . . . . . . . . . . 121 10.5.2 spi status register (spsr) . . . . . . . . . . . . . . . . . . . . . . . 123 10.5.3 spi data i/o register (spdat) . . . . . . . . . . . . . . . . . . . . 124 10.6 spi during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.2 introduction the spi is a synchronous interface which allows several spi microcontrollers or spi-type peripherals to be interconnected. in a serial peripheral interface, separate wires (signals) are required for data and clock. in the spi format, the clock is not included in the data stream and must be furnished as a separate signal. the mc68hc(7)05h12 spi system may be configured either as a master or as a slave.
non-disclosure agreement required serial peripheral interface (spi) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 116 serial peripheral interface (spi) motorola features include: full-duplex, 3-wire synchronous transfers master or slave operation 2.50 mhz (maximum) master bit frequency 5.0 mhz (maximum) slave bit frequency four programmable master bit rates programmable clock polarity and phase end-of-transmission interrupt flag write collision flag protection master-master mode fault protection easy interface to simple expansion parts (plls, d/as, latches, display drivers, etc.) very low clock rates by reuse of the sci prescalers. 10.3 spi signal description three i/o pins located at port b are associated with the spi data transfers. they are the serial clock (sck), the master in/slave out (miso) data line, the master out/slave in (mosi) data line. when the spi system is not utilized (spe bit cleared in the serial peripheral control register), the three pins (miso, mosi, sck) are configured as general- purpose i/o pins. the three spi signals are discussed in the following paragraphs for both master mode and slave mode of operation. note: the spi subsystem works as master and does not have a slave select input line (ss). 10.3.1 master in slave out (miso) the miso line is configured as an input in a master device and as an output in a slave device. it is one of the two lines that transfer serial data in one direction, with the most significant bit sent first. the miso line of a slave device is placed in the high-impedance state if the slave is not selected.
serial peripheral interface (spi) spi signal description mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial peripheral interface (spi) 117 non-disclosure agreement required 10.3.2 master out slave in (mosi) the mosi line is configured as an output in a master device and as an input in a slave device. it is one of the two lines that transfer serial data in one direction with the most significant bit sent first. 10.3.3 serial clock (sck) the serial clock is used to synchronize data movement both in and out of the device through its mosi and miso lines. the master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. since sck is generated by the master device, this line becomes an input on a slave device. as shown in figure 10-1 , four different timing relationships may be selected by control bits cpol and cpha in the serial peripheral control register (spcr). both master and slave devices must operate with the same timing. the master device always places data on the mosi line a half cycle before the clock edge (sck), in order for the slave device to latch the data. two bits (spr0 and spr1) in the spcr of the master device select the clock rate. in a slave device, spr0 and spr1 have no effect on the operation of the spi.
non-disclosure agreement required serial peripheral interface (spi) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 118 serial peripheral interface (spi) motorola figure 10-1. data clock timing diagram msb 6 54321 lsb internal strobe for data capture (all modes) miso / mosi sck sck sck sck (cpol = 0, cpha = 0) (cpol = 0, cpha = 1) (cpol = 1, cpha = 0) (cpol = 1, cpha = 1)
serial peripheral interface (spi) spi functional description mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial peripheral interface (spi) 119 non-disclosure agreement required 10.4 spi functional description figure 10-2. serial peripheral block diagram figure 10-2 shows a block diagram of the serial peripheral interface circuitry. when a master device transmits data to a slave device via the mosi line, the slave device responds by sending data to the master device via the master? miso line. this implies full duplex transmission with both data out and data in synchronized to the same clock signal. thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmitter-empty and receiver-full divider ? 2 ? 4 ? 16 ? 32 select 8-bit shift reg read data buff msb lsb s m m s s m pin control logic clock clock logic spi clock mstr spe spie spe mstr cpol cpha spr1 spr0 spi control register internal data bus spi interrupt request spi status register spr1 spr0 spi control spif wcol modf internal mcu clock pb7/ pb6/ pb5/ miso mosi sck (master) sci clock dod
non-disclosure agreement required serial peripheral interface (spi) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 120 serial peripheral interface (spi) motorola status bits. a single status bit (spif) is used to signify that the i/o operation has been completed. the spi is double buffered on read, but not on write. if a write is performed during data transfer, the transfer is not interrupted, and the write will be unsuccessful. this condition will cause the write collision status bit (wcol) in the spsr to be set. after a data byte is shifted, the spif flag in the spsr is set. in master mode, the sck pin is an output. it idles high or low, depending on the cpol bit in the spcr, until data is written to the shift register. then eight clocks are generated to shift the eight bits of data, after which sck goes idle again. in slave mode, the slave start logic receives a clock input at the sck pin. thus, the slave is synchronized to the master. data from the master is received serially via the slave mosi line and is loaded into the 8-bit shift register. the data is then transferred, in parallel, from the 8-bit shift register to the read buffer. during a write cycle, data is written into the shift register, then the slave waits for a clock train from the master to shift the data out on the slave? miso line. figure 10-3 illustrates the mosi, miso and sck master-slave interconnections. figure 10-3. serial peripheral interface master-slave interconnection 8-bit shift register 8-bit shift register miso mosi miso mosi spi clock generator sck sck slave master
serial peripheral interface (spi) registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial peripheral interface (spi) 121 non-disclosure agreement required 10.5 registers there are three registers in the serial peripheral interface which provide control, status and data storage functions. these registers are called the serial peripheral control register (spcr), the serial peripheral status register (spsr) and the serial peripheral data i/o register (spdat). 10.5.1 spi control register (spcr) spie ?spi interrupt enable when this bit is set to one, a hardware interrupt sequence is requested each time the spif or modf status flag is set. spi interrupts are inhibited if this bit is clear or if the i bit in the cc register is set. 1 = spi interrupts enabled 0 = spi interrupts disabled spe ?spi system enable 1 = spi system on 0 = spi system off dod ?direction of data flow (in or out of the serial shift register) 1 = data is transferred lsb first 0 = data is transferred msb first mstr ?master/slave mode select 1 = master mode 0 = slave mode $0044 bit 7 654321 bit 0 read: spie spe dod mstr cpol cpha spr1 spr0 write: reset: 000001uu figure 10-4. spi control register (spcr)
non-disclosure agreement required serial peripheral interface (spi) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 122 serial peripheral interface (spi) motorola cpol ?clock polarity when the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the sck pin of the master device. conversely, if this bit is set, the sck pin will idle high. this bit is also used in conjunction with the clock phase control bit to produce the desired clock-data relationship between master and slave. see figure 10-1 . cpha ?clock phase the clock phase bit, in conjunction with the cpol bit, controls the clock-data relationship between master and slave. the cpol bit can be thought of simply as inserting an inverter in series with the sck line. the cpha bit selects one of two fundamentally different clocking protocols. refer to figure 10-1 . spr1, spr0 ?spi clock rate selects if the device is a master, the two serial peripheral rate bits select one of four division ratios of the input-clock to be used as sck (see table 10-1 ). these bits have no effect in slave mode. bit 6 (spp = spi prescaler) of the sci baud rate register, section 11.8.5 baud rate register (baud) , determines the input clock of the spi module. spp ?spi prescaler 1 = sci receiver clock connected to the spi clock input 0 = bus clock connected to the spi clock input note: if spp is set, the spi clock rate is dependent on the sci clock rate. the spi clock rate is given by e: prs1: prs2: prs0. prs1 and prs2 are table 10-1. spi clock rate selection spr1 spr0 input clock divided by prs0 00 2 01 4 10 16 11 32
serial peripheral interface (spi) registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial peripheral interface (spi) 123 non-disclosure agreement required the sci prescaler factors given in table 11-1 and table 11-2 . prs0 is the spi prescaler factor given in table 10-1 . 10.5.2 spi status register (spsr) spif ?spi interrupt request flag the serial peripheral data transfer flag bit is set after the eighth sck cycle in a data transfer and it is cleared by reading the spsr register (with spif set) followed by reading from or writing to the spi data register (spdat). wcol ?write collision the write collision bit is used to indicate that a serial transfer was in progress when the mcu tried to write new data into the spdat data register. the mcu write is disabled to avoid writing over the data being transmitted. no interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the time of the error. this flag is automatically cleared by a read of the spsr (with wcol set) followed by an access (read or write) to the spdat register. $0045 bit 7 654321 bit 0 read: spif wcol 000000 write: reset: 00000000 figure 10-5. spi status register (spsr)
non-disclosure agreement required serial peripheral interface (spi) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 124 serial peripheral interface (spi) motorola 10.5.3 spi data i/o register (spdat) the serial peripheral data i/o register is used to transmit and receive data on the serial bus. only a write to this register will initiate transmission/reception of another byte, and this will only occur in the master device. at the completion of transmitting a byte of data, the spif status bit is set in both the master and slave devices. when the user reads the serial peripheral data i/o register, a buffer is actually being read. the first spif must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated or an overrun condition will exist. in cases of overrun, the byte which causes the overrun is lost. a write to the serial peripheral data i/o register is not buffered and places data directly into the shift register for transmission. 10.6 spi during wait mode when the mcu enters wait mode, the cpu clock is halted. all cpu action is suspended; however, the spi system remains active. in fact an interrupt from the spi causes the processor to exit the wait mode. $0046 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: uuuuuuuu figure 10-6. spi data i/o register (spdat)
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial communications interface (sci) 125 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 11. serial communications interface (sci) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.4 receiver wake-up operation . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.4.1 idle line wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.4.2 address mark wake-up. . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.5 receive data (rdi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.6 start bit detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.7 transmit data (tdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.8 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.8.1 serial communications data register (scdat). . . . . . . . 135 11.8.2 serial communications control register 1 (sccr1) . . . . 136 11.8.3 serial communications control register 2 (sccr2) . . . . 137 11.8.4 serial communications status register (scsr) . . . . . . . 138 11.8.5 baud rate register (baud) . . . . . . . . . . . . . . . . . . . . . . . 140 11.9 sci during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.2 introduction the sci is a full-duplex uart-type asynchronous system, using standard non return-to-zero (nrz) format (one start bit, eight or nine data bits, and a stop bit). an on-chip baud-rate generator derives standard baud-rate frequencies from the mcu oscillator. both the transmitter and the receiver are double buffered; thus, back-to-back characters can be handled easily, even if the central processing unit (cpu) is delayed in responding to the completion of an individual character. the sci transmitter and receiver are functionally independent but use the same format and baud rate.
non-disclosure agreement required serial communications interface (sci) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 126 serial communications interface (sci) motorola sci two-wire system features: standard nrz (mark/space) format. advanced error detection method includes noise detection for noise duration of up to 1/16th bit time. full-duplex operation. software programmable for one of 32 different baud rates. software selectable word length (eight or nine bit words). separate transmitter and receiver enable bits. capable of being interrupt driven. four separate enable bits available for interrupt control. sci receiver features: receiver wake-up function (idle line or address bit). idle line detect. framing error detect. noise detect. overrun detect. receiver data register full flag. sci transmitter features: transmit data register empty flag. transmit complete flag. send break. a block diagram of the sci is shown in figure 11-1 . the user has option bits in serial communication control register 1 (sccr1) to select the ?ake-up?method (wake bit) and data word length (m bit) of the sci. serial communications control register 2 (sccr2) provides control bits which individually enable/disable the transmitter or receiver (te and re, respectively), enable system interrupts (tie, tcie, rie, ilie) and provide the wake-up enable bit (rwu) and the send break code bit
serial communications interface (sci) introduction mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial communications interface (sci) 127 non-disclosure agreement required (sbk). control bits in the baud rate register (baud) allow the user to select one of 32 different baud rates for the transmitter and receiver.
non-disclosure agreement required serial communications interface (sci) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 128 serial communications interface (sci) motorola figure 11-1. serial communications interface block diagram sci interrupt internal bus receive data register (see note) receive data shift register sccr2 tie tcie rie ilie te re sbk rwu 2 7 te sbk fe nf or dle rdrf tc tdre scsr $4a wake-up unit transmit control flag control receive control rate generator internal processor data tclr spp scp1 scp0 rckb scr2 scr1 scr0 baud $4b r8 t8 0 m wake 0 0 sccr1 $48 tdo transmit data shift register transmit data register (see note) $47 $47 rdi $49 0
serial communications interface (sci) introduction mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial communications interface (sci) 129 non-disclosure agreement required note: the serial communications data register (scdat) is controlled by the internal r/w signal. it is the transmit data register when written and the receive data register when read. data transmission is initiated by a write to the serial communications data register (scdr). provided the transmitter is enabled, data stored in the scdr is transferred to the transmit data shift register. this transfer of data sets the transmit data register empty flag (tdre) in the sci status register (scsr) and may generate an interrupt if the transmit interrupt is enabled. the transfer of data to the transmit data shift register is synchronized with the bit rate clock. all data is transmitted least significant bit first. upon completion of data transmission, the transmission complete flag (tc) in the scsr is set (provided no pending data, preamble or break is to be sent), and an interrupt may be generated if the transmit complete interrupt is enabled. if the transmitter is disabled, and the data, preamble or break (in the transmit data shift register) has been sent, the tc bit will also be set. this will also generate an interrupt if the transmission complete interrupt enable bit (tcie) is set. if the transmitter is disabled in the middle of a transmission, that character will be completed before the transmitter gives up control of the tdo pin. when scdr is read, it contains the last data byte received, provided that the receiver is enabled. the receive data register full flag bit (rdrf) in the scsr is set to indicate that a data byte has been transferred from the input serial shift register to the scdr, which can cause an interrupt if the receiver interrupt is enabled. the data transfer from the input serial shift register to the scdr is synchronized by the receiver bit rate clock. the or (overrun), nf (noise), or fe (framing) error flags in the scsr may be set if data reception errors occurred. an idle line interrupt is generated if the idle line interrupt is enabled and the idle bit (which detects idle line transmission) in scsr is set. this allows a receiver that is not in the wake-up mode to detect the end of a message or the preamble of a new message, or to resynchronize with the transmitter. a valid character must be received before the idle line condition or the idle bit will not be set and idle line interrupt will not be generated.
non-disclosure agreement required serial communications interface (sci) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 130 serial communications interface (sci) motorola 11.3 data format receive data or transmit data is the serial data that is transferred to the internal data bus from the receive data input pin (rdi) or from the internal bus to the transmit data output pin (tdo). the non-return-to- zero (nrz) data format shown in figure 11-2 is used and must meet the following 5 criteria: 1. the idle line is brought to a logic one state prior to transmission/reception of a character. 2. a start bit (logic zero) is used to indicate the start of a frame. 3. the data is transmitted and received least significant bit first. 4. a stop bit (logic one) is used to indicate the end of a frame. a frame consists of a start bit, a character of eight or nine data bits, and a stop bit. 5. a break is defined as the transmission or reception of a low (logic zero) for at least one complete frame time. figure 11-2. data format 11.4 receiver wake-up operation the receiver logic hardware also supports a receiver wake-up function which is intended for systems having more than one receiver. with this function a transmitting device directs messages to an individual receiver or group of receivers by passing addressing information as the initial byte(s) of each message. the wake-up function allows receivers not 0 1 2 3 4 5 6 7 8 stop start 0 start idle line control bit ? selects 8 or 9 bit data { optional
serial communications interface (sci) receiver wake-up operation mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial communications interface (sci) 131 non-disclosure agreement required addressed to remain in a dormant state for the remainder of the unwanted message. this eliminates any further software overhead to service the remaining characters of the unwanted message and thus improves system performance. the receiver is placed in wake-up mode by setting the receiver wake-up bit (rwu) in the sccr2 register. while rwu is set, all of the receiver related status flags (rdrf, idle, or, nf, and fe) are inhibited (cannot become set). note that the idle line detect function is inhibited while the rwu bit is set. although rwu may be cleared by a software write to sccr2, it would be unusual to do so. normally rwu is set by software and gets cleared automatically with hardware by one of the two methods described below. 11.4.1 idle line wake-up in idle line wake-up mode, a dormant receiver wakes up as soon as the rdi line becomes idle. idle is defined as a continuous logic high level on the rdi line for ten (or eleven) full bit times. systems using this type of wake-up must provide at least one character time of idle between messages to wake up sleeping receivers, but must not allow any idle time between characters within a message. 11.4.2 address mark wake-up in address mark wake-up, the most significant bit (msb) in a character is used to indicate that the character is an address (1) or a data (0) character. sleeping receivers will wake up whenever an address character is received. systems using this method for wake-up would set the msb of the first character of each message and leave it clear for all other characters in the message. idle periods may be present within messages and no idle time is required between messages for this wake- up method.
non-disclosure agreement required serial communications interface (sci) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 132 serial communications interface (sci) motorola 11.5 receive data (rdi) receive data is the serial data that is applied through the input line and the serial communications interface to the internal bus. the receiver circuitry clocks the input at a rate equal to 16 times the baud rate and this time is referred to as the rt clock. once a valid start bit is detected the start bit, each data bit and the stop bit are sampled three times at rt intervals 8 rt, 9 rt and 10 rt (1 rt is the position where the bit is expected to start), as shown in figure 11- 3 . the value of the bit is determined by voting logic which takes the value of the majority of the samples. figure 11-3. sampling technique used on all bits 11.6 start bit detection when the rdi input is detected low, it is tested for three more sample times (referred to as the start edge verification samples in figure 11-4 ). if at least two of these three verification samples detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. a noise flag is set if all three verification samples do not detect a logic zero. a valid start bit could be assumed with a set noise flag present. if there has been a framing error without detection of a break (10 zeros for 8-bit format or 11 zeros for 9-bit format), the circuit continues to operate as if there actually was a stop bit and the start edge will be placed artificially. the last bit received in the data shift register is previous bit present bit samples next bit rdi v v v 16 r t 1 r t 8 r t 9 r t 10 r t 16 r t 1 r t
serial communications interface (sci) start bit detection mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial communications interface (sci) 133 non-disclosure agreement required inverted to a logic one, and the three logic one start qualifiers (shown in figure 11-4 ) are forced into the sample shift register during the interval when detection of a start bit is anticipated (see figure 11-5 ); therefore, the start bit will be accepted no sooner than it is anticipated. if the receiver detects that a break produced the framing error, the start bit will not be artificially induced and the receiver must actually detect a logic one before the start bit can be recognised (see figure 11-6 ). figure 11-4. examples of start bit sampling techniques 16x internal sampling clock rt clock edges (for all three examples) 1 r t 2 r t 3 r t 4 r t 5 r t rdi idle start 000 start verification 1 1 1 1 1 1 1 1 1 1 start qualifiers 1 0 0 1 1 1 1 1 1 1 1 1 1 rdi idle start noise idle noise rdi start 000 1 1 1 1 1 0 1 1 1 1
non-disclosure agreement required serial communications interface (sci) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 134 serial communications interface (sci) motorola figure 11-5. sci artificial start following a framing error figure 11-6. sci start bit following a break data samples receive data in data expected stop artificial edge start bit data (a) case 1, receive line low during artificial edge data samples receive data in data expected stop start bit data start edge (b) case 2, receive line high during expected start edge expected stop break receive data in data samples start qualifiers start edge verification samples start bit detected a start edge
serial communications interface (sci) transmit data (tdo) mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial communications interface (sci) 135 non-disclosure agreement required 11.7 transmit data (tdo) transmit data is the serial data from the internal data bus that is applied through the serial communications interface to the output line. the transmitter generates a bit time by using a derivative of the rt clock, thus producing a transmission rate equal to 1/16th that of the receiver sample clock. 11.8 registers primarily the sci system is configured and controlled by five registers baud, sccr1, sccr2, scsr, and scdat. 11.8.1 serial communications data register (scdat) the sci data register (scdat) shown in figure 11-7 is actually two separate registers. when scdat is read, the read-only receive data register is accessed and when scdat is written, the write-only transmit data register is accessed. $0047 bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: uuuuuuuu figure 11-7. sci data register (scdat)
non-disclosure agreement required serial communications interface (sci) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 136 serial communications interface (sci) motorola 11.8.2 serial communications control register 1 (sccr1) r8 ?receive data bit 8 this bit is the ninth serial data bit received when the sci system is configured for nine data bit operation (m = 1). the most significant bit (bit 8) of the received character is transferred into this bit at the same time as the remaining eight bits (bits 0 ?7) are transferred from the serial receive shift register to the sci receive data register. t8 ?transmit data bit 8 this bit is the ninth data bit to be transmitted when the sci system is configured for nine data bit operation (m = 1). when the eight low order bits (bits 0?) of a transmit character are transferred from the sci data register to the serial transmit shift register, this bit (bit 8) is transferred to the ninth bit position of the shift register. m ?mode (select character format) the m bit controls the character length for both the transmitter and receiver at the same time. the 9th data bit is most commonly used as an extra stop bit or in conjunction with the ?ddress mark?wake-up method. it can also be used as a parity bit. 1 = 1 start bit, 8 data bits + 9th data bit, 1 stop bit 0 = 1 start bit, 8 data bits, 1 stop bit wake ?wake-up mode select 1 = wake-up on address mark 0 = wake-up on idle line $0048 bit 7 654321 bit 0 read: r8 t8 0 m wake 000 write: reset: uuuuuuuu figure 11-8. sci control register 1 (sccr1)
serial communications interface (sci) registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial communications interface (sci) 137 non-disclosure agreement required 11.8.3 serial communications control register 2 (sccr2) the sci control register 2 (sccr2) provides the control bits that enable/disable individual sci functions. tie ?transmit interrupt enable 1 = sci interrupt if tdre = 1 0 = tdre interrupts disabled tcie ?transmit complete interrupt enable 1 = sci interrupt if tc = 1 0 = tc interrupts disabled rie ?receiver interrupt enable 1 = sci interrupt if rdrf or or = 1 0 = rdrf and or interrupts disabled ilie ?idle line interrupt enable 1 = idle line interrupt enable 0 = idle interrupts disabled te ?transmitter enable when the transmit enable bit is set, the transmit shift register output is applied to the tdo line. depending on the state of control bit m (sccr1), a preamble of 10 (m = 0) or 11 (m = 1) consecutive ones is transmitted when software sets the te bit from a cleared state. after loading the last byte in the serial communications data register and receiving the tdre flag, the user can clear te. transmission of the last byte will then be completed before the transmitter gives up control of the tdo pin. while the transmitter is active, the port c bit 7 line is forced to be an output. $0049 bit 7 654321 bit 0 read: tie tcie rie ilie te re rwu sbk write: reset: 00000000 figure 11-9. sci control register 2 (sccr2)
non-disclosure agreement required serial communications interface (sci) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 138 serial communications interface (sci) motorola re ?receiver enable when the receiver enable bit is set, the receiver is enabled. when re is clear, the receiver is disabled and all of the status bits associated with the receiver (rdrf, idle, or, nf and fe) are inhibited. while the receiver is enabled, the port c bit 6 is forced to be an input. rwu ?receiver wake-up when the receiver wake-up bit is set by the user software, it puts the receiver to sleep and enables the wake-up function. if the wake bit is cleared, rwu is cleared by the sci logic after receiving 10 (m = 0) or 11 (m = 1) consecutive ones. if the wake bit is set, rwu is cleared by the sci logic after receiving a data word whose msb is set. sbk ?send break if the send break bit is toggled set and cleared, the transmitter sends 10 (m = 0) or 11 (m = 1) zeros and then reverts to idle sending data. if sbk remains set, the transmitter will continually send whole blocks of zeros (sets of 10 or 11) until cleared. at the completion of the break code, the transmitter sends at least one high bit to guarantee recognition of a valid start bit. if the transmitter is currently empty and idle, setting and clearing sbk is likely to queue two character times of break because the first break transfers almost immediately to the shift register and the second is then queued into the parallel transmit buffer. 11.8.4 serial communications status register (scsr) the serial communications status register (scsr) provides inputs to the interrupt logic circuits for generation of the sci system interrupt. $004a bit 7 654321 bit 0 read: tdre tc rdrf idle or nf fe 0 write: reset: 11000000 figure 11-10. sci status register (scsr)
serial communications interface (sci) registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial communications interface (sci) 139 non-disclosure agreement required tdre ?transmit data register empty flag this bit is set when the byte in the transmit data register is transferred to the serial shift register. new data will not be transmitted unless the scsr register is read before writing to the transmit data register. reset sets this bit. tc ?transmit complete flag this bit is set to indicate that the sci transmitter has no meaningful information to transmit (no data in shift register, no preamble, no break). when tc is set the serial line will go idle (continuous mark). reset sets this bit. rdrf -?receive data register full flag this bit is set when the contents of the receiver serial shift register is transferred to the receiver data register. idle ?idle line detected flag this bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven consecutive ??). this bit will not be set by the idle line condition when the rwu bit is set. once cleared, idle will not be set again until after rdrf has been set, (until after the line has been active and becomes idle again). or ?overrun error flag this bit is set when a new byte is ready to be transferred from the receiver shift register to the receiver data register and the receive data register is already full (rdrf bit is set). data transfer is inhibited until this bit is cleared. nf ?noise error flag this bit is set if there is noise on a ?alid?start bit, any of the data bits, or on the stop bit. the nf bit is set during the same cycle as the rdrf bit but does not get set in the case of an overrun (or). fe ?framing error flag this bit is set when the word boundaries in the bit stream are not synchronized with the receiver bit counter (generated by the reception of a logic zero bit where a stop bit was expected). the fe bit reflects the status of the byte in the receive data register and the transfer from
non-disclosure agreement required serial communications interface (sci) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 140 serial communications interface (sci) motorola the receive shift register to the receive data register is inhibited in the case of overrun. the fe bit is set during the same cycle as the rdrf bit but does not get set in the case of an overrun (or). the framing error flag inhibits further transfer of data into the receive data register until it is cleared. 11.8.5 baud rate register (baud) the baud rate register (baud) is used to set the bit rate for the sci system. normally this register is written once, during initialization, to set the baud rate for sci communications. both the receiver and the transmitter use the same baud rate which is derived from the mcu bus rate clock. a two stage divider is used to develop custom baud rates from normal mcu crystal frequencies so it is not necessary to use special baud rate crystal frequencies. tclr ?clear baud rate counters (for test purposes only) this bit is disabled and remains low in any mode other than test or bootstrap mode. reset clears this bit. while in test or bootstrap mode, setting this bit causes the baud rate counter chains to be reset. the logic one state of this bit is transitory and reads always return a logic zero. this control bit is intended only for factory testing of the mcu. spp ?spi prescaler bit 1 = sci receiver clock connected to the spi clock input. 0 = bus clock connected to the spi clock input. the sci baud rate can be calculated from the internal bus clock and the two prescaler factors prs1 and prs2. the first prescaler factor prs1 is selected with scp0 and scp1, as shown in table 11-1 . the $004b bit 7 654321 bit 0 read: 0 spp scp1 scp0 0 scr2 scr1 scr0 write: tclr rckb reset: 11000uuu figure 11-11. sci baud rate register (baud)
serial communications interface (sci) registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola serial communications interface (sci) 141 non-disclosure agreement required second prescaler factor prs2 is selected with scr0, scr1 and scr2, as shown in table 11-2 . the sci baud rate b equals the internal bus clock divided by 16 divided by prs1 divided by prs2, [b = bus clock: 16: prs1: prs2]. scp1, scp0 ?first serial prescaler select bits scr2, scr1, scr0 ?sci rate select bits of the second prescaler stage these three bits select the baud rates for both the transmitter and the receiver. rckb ?sci receive baud rate clock test this bit is disabled and remains low in any mode other than test or bootstrap modes. reset clears this bit. while in test or bootstrap mode, this bit may be written but not read (reads always return a logic zero). setting this bit enables a baud rate counter test mode where table 11-1. first prescaler stage scp1 scp0 prs1 001 013 104 1113 table 11-2. second prescaler stage scr2 scr1 scr0 prs2 0001 0012 0104 0118 10016 10132 11064 111128
non-disclosure agreement required serial communications interface (sci) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 142 serial communications interface (sci) motorola the exclusive-or of the receiver clock (16 times the baud rate) and the transmit clock (1 times the baud rate) is driven out the pc3/tdo pin. this control bit is intended only for factory testing of the mcu. 11.9 sci during wait mode the sci system is not affected by the wait mode and continues regular operation. any valid sci interrupt will wake the system up.
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola analog to digital converter 143 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 12. analog to digital converter 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.3 a/d principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.4 a/d operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.5 internal and master oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 145 12.6 a/d registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.6.1 a/d status and control register (adscr) . . . . . . . . . . . . 146 12.6.2 a/d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.7 a/d during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.8 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.9 conversion accuracy definitions . . . . . . . . . . . . . . . . . . . . . . 150 12.9.1 transfer curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.9.2 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.9.3 quantization error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.4 offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.5 gain scale error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.6 differential linearity error . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.7 integral linearity error. . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9.8 total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
non-disclosure agreement required analog to digital converter general release speci?ation mc68hc(7)05h12 ? rev. 1.0 144 analog to digital converter motorola 12.2 introduction the analog to digital converter system consists of a single 8-bit successive approximation converter and a channel multiplexer. there is one 8-bit result data register and one 8-bit status/control register. the reference supply for the converter uses two dedicated pins rather than being driven by the system power supply lines, because the voltage drops in the bonding wires of such heavily loaded pins would decrease the accuracy of the a/d conversion. an internal rc type oscillator is activated by the adrc bit in the a/d status/control register. this rc oscillator is used to give sufficiently high clock rate to the a/d when the bus speed is too low for the a/d to be accurate. additionally, the adon bit allows the user to disconnect the a/d when not used, in order to save power. this is particularly useful to reduce current consumption (by typically 100 m a) when going into the wait mode. the a/d is ratiometric and two dedicated pins supply the reference voltage (vrefh and vrefl). an input voltage equal to or greater than vrefh converts to $ff (full scale) with no overflow indication (if greater). an input voltage equal to vrefl converts to $00. for ratiometric conversions, the source of each analog input should use vrefh as the supply voltage and be referenced to vrefl. 12.3 a/d principle the a/d reference inputs are applied to a precision internal digital to analog converter. control logic drives this d/a and the analog output is successively compared to the selected analog input which was sampled at the beginning of the conversion time. the conversion is monotonic with no missing codes. the 8-bit conversions are accurate to within 1.5 lsb including quantization.
analog to digital converter a/d operation mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola analog to digital converter 145 non-disclosure agreement required 12.4 a/d operation the a/d is an 8-bit s.a.r. type a/d converter, with continuous conversion per given channel. the result of a conversion is loaded into the read-only result data register, and a conversion complete flag coco is set in the a/d status/control register. any write to the a/d status/control register will abort the current conversion, reset the conversion complete flag and start a new conversion on the selected channel. at power-on or external reset, both the adrc and adon bits are cleared. thus the a/d is disabled. each channel of conversion takes 32 clock cycles, which must be at a frequency equal to or greater than 1 mhz. a multiplexer allows the single a/d converter to select one of four external analog signals and three internal reference sources. 12.5 internal and master oscillator if the mcu bus (e clock) frequency is less than 1.0 mhz, an internal rc oscillator (nominally 1.5 mhz) must be used for the a/d conversion clock. this selection is made by setting the adrc bit in the a/d status/control register to 1. when the internal rc oscillator is being used as the conversion clock three limitations apply: 1. the conversion complete flag (coco) must be used to determine when a conversion sequence has been completed, due to the frequency tolerance of the rc oscillator and its asynchronism with regard to the mcu bus clock. 2. the conversion process runs at the nominal 1.5 mhz rate, but the conversion results must be transferred to the mcu result registers synchronously with the mcu bus clock, so the conversion time is limited to a maximum of one channel per bus cycle. 3. if the system clock is running faster than the rc oscillator, the rc oscillator should be turned off, and the system clock used as the conversion clock.
non-disclosure agreement required analog to digital converter general release speci?ation mc68hc(7)05h12 ? rev. 1.0 146 analog to digital converter motorola 12.6 a/d registers 12.6.1 a/d status and control register (adscr) coco ?conversions complete this read-only status bit is set when a conversion is completed, indicating that the a/d data register contains valid results. this bit is cleared whenever the a/d status/control register is written and a new conversion automatically started, or whenever the a/d register is read. once a conversion has been started by writing to the a/d status/control register, conversions of the selected channel will continue every 32 cycles until the a/d status/control register is written to again. in this continuous conversion mode the a/d data register will be filled with new data, and the coco bit set, every 32 cycles. data from the previous conversion will be overwritten regardless of the state of the coco bit prior to writing. adrc ?rc oscillator on when adrc is set, the a/d section runs on the internal rc oscillator instead of the cpu clock. the rc oscillator requires a time t rcon to stabilize, and results can be inaccurate during this time. see section 12.5 internal and master oscillator . adon ?a/d on when the a/d is turned on (adon = 1), it requires a time t adon for the current sources to stabilize, and results can be inaccurate during this time. this bit turns on the charge pump. $004f bit 7 654321 bit 0 read: coco adrc adon 0 ch3 ch2 ch1 ch0 write: reset: 00000000 figure 12-1. a/d status and control register (adscr)
analog to digital converter a/d registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola analog to digital converter 147 non-disclosure agreement required ch3? ?channel select bit ch3, ch2, ch1 and ch0 form a four bit field which is used to select one of sixteen a/d channels. channels 4?5 are used for internal reference points. the following table shows the signals selected by the channel select field. note: performing a digital read of the a/d input with levels other than vdd or vss on the adin pins will result in greater power dissipation during the read cycle, and may give hazardous results on the adin input table 12-1. a/d clock selection adrc adon comments 0 0 rc oscillator off, a/d converter off. 0 1 rc oscillator off, a/d converter on. 10 rc oscillator on, a/d converter off. gives time for the rc osc to stabilize. 1 1 rc oscillator on, a/d converter on.a/d using rc osc clocks table 12-2. a/d channel assignments ch3 ch2 ch1 ch0 channel signal 00000 an0 00011 an1 00102 an2 00113 an3 01004 v refl 01015 v refl 01006 v refl 01117 v refl 10008 v refh 10019(v refh +v refl )/2 101010 v refl 101111 v refl 1 1 x x 12-15 v refl
non-disclosure agreement required analog to digital converter general release speci?ation mc68hc(7)05h12 ? rev. 1.0 148 analog to digital converter motorola 12.6.2 a/d data register one 8-bit result register is provided. this register is updated each time coco is set. 12.7 a/d during wait mode the a/d converter continues normal operation during wait mode. to decrease power consumption during wait, it is recommended that both the adon and adrc bits in the a/d status/control register be cleared if the a/d converter is not being used. if the a/d converter is in use and the system clock rate is above 1.0 mhz, it is recommended that the adrc bit be cleared. note: as the a/d converter continues to function normally in wait mode, the coco bit is not cleared. 12.8 analog input the external analog voltage value to be converted by the a/d converter is sampled on an internal capacitor through a resistive path provided by input-selection switches and a sampling aperture time switch. sampling time is limited to 12 bus clock cycles. after sampling, the analog value is stored on a capacitor and held until the end of conversion. during this hold time, the analog input is disconnected from the internal a/d system and the external voltage source sees a high impedance input. the equivalent analog input during sampling is a rc low-pass filter with resistance around 50 k w and a capacitance of around 10pf. (it should be noted that these are typical values measured at room temperature). $004e bit 7 654321 bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: uuuuuuuu figure 12-2. a/d data register (addr)
analog to digital converter analog input mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola analog to digital converter 149 non-disclosure agreement required figure 12-3. electrical model of an a/d input pin * * this analog switch is closed only during the 12-cycle sample time input protection diffusion analog input dac capacitance > 50 k w 10 pf +~ 20 v < 2pf vrefl / vss
non-disclosure agreement required analog to digital converter general release speci?ation mc68hc(7)05h12 ? rev. 1.0 150 analog to digital converter motorola 12.9 conversion accuracy definitions this section explains the terminology used to specify the analog characteristics of the a/d converter. 12.9.1 transfer curve the ideal transfer curve can be thought of as a staircase of uniform step size with perfect positioning of the endpoints. figure 12-4 shows the ideal transfer curve of an 8-bit a/d converter. figure 12-4. transfer curve of an ideal 8-bit a/d converter 12.9.2 monotonicity the characteristic of the transfer function whereby increasing the input signal results in the output never decreasing. input voltage (lsb) conversion result $00 $01 $02 $03 $fd $fe $ff 1 2 3 254 255 1lsb = vrefh / 256 1-bit accuracy 253
analog to digital converter conversion accuracy definitions mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola analog to digital converter 151 non-disclosure agreement required 12.9.3 quantization error also known as digitization error or uncertainty. it is the inherent error involved in digitizing an analog signal due to the finite number of steps at the digital output versus the infinite number of values at the analog input. 12.9.4 offset error the offset error is the dc shift of the entire transfer curve of an ideal converter. 12.9.5 gain scale error the gain error is an error in the input to output transfer ratio. gain error causes an error in the slope of the transfer curve. 12.9.6 differential linearity error the differential linearity error is the difference between actual analog voltage change and the ideal (1lsb) voltage change at any code change. 12.9.7 integral linearity error the integral linearity error is the departure from the best fitting line through all a/d code changes. this error is not specified from the ideal line to make this error independent from offset and gain errors causes an error in the slope of the transfer curve. 12.9.8 total unadjusted error the total unadjusted error is the maximum error that occurs without adjusting offset and gain errors. this error is a combination of offset, scale and integral linearity errors.
non-disclosure agreement required analog to digital converter general release speci?ation mc68hc(7)05h12 ? rev. 1.0 152 analog to digital converter motorola
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola eeprom 153 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 13. eeprom 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.3 eeprom control register (eepcr) . . . . . . . . . . . . . . . . . . . 154 13.4 eeprom options register (eeopr) . . . . . . . . . . . . . . . . . . 155 13.5 eeprom read, erase and programming procedures . . . . . 156 13.5.1 read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13.5.2 erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13.5.3 programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.6 operation in wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.2 introduction the eeprom on this device is 256 bytes and is located from address $0400 to $04ff. programming the eeprom can be done by the user on a single-byte basis by manipulating the eeprom control register (eepcr). an erased byte reads as ?f?and any programmed bit reads as ??
non-disclosure agreement required eeprom general release speci?ation mc68hc(7)05h12 ? rev. 1.0 154 eeprom motorola 13.3 eeprom control register (eepcr) eeosc ?eeprom rc oscillator control when this bit is set, the eeprom section uses the internal rc oscillator instead of the cpu clock. after setting the eeosc bit, delay a time t rcon to allow the rc oscillator to stabilize. this bit is readable and writable and should be set by the user when the internal bus frequency falls below 1.5 mhz. reset clears this bit. eer1, eer0 ?erase select bits eer1 and eer0 form a 2-bit field which is used to select one of three erase modes: byte, block, or bulk erase. table 13-1 shows the modes selected for each bit configuration. these bits are readable and writable and are cleared by reset. in byte erase mode, only the selected byte is erased. in block mode, a 128-byte block of eeprom is erased. the eeprom memory space is divided into two 128-byte blocks ($0400?047f, $0480?04ff), and doing a block erase to any address within a block will erase the entire block. in bulk erase mode, the entire 256 byte eeprom section is erased. a block protect function is available on block 2 of the eeprom memory space. see section 13.4 eeprom options register (eeopr) for more details. $001c bit 7 654321 bit 0 read: 0 0 0 eeosc eer1 eer0 eelat eepgm write: reset: 00000000 figure 13-1. eeprom control register (eepcr) table 13-1. erase mode select eer1 eer0 mode 00 no erase 01 byte erase 10 block erase (block1 or block2) 11 bulk erase (block1 & block2)
eeprom eeprom options register (eeopr) mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola eeprom 155 non-disclosure agreement required eelat ?eeprom programming latch the eelat bit is the eeprom programming latch enable. when eelat is at ?ero? the eer1, eer0 and eepgm bits are reset to zero. when the eelat bit is clear, data can be read from the eeprom, and when set, this bit allows the address and data to be latched into the eeprom for further programming or erase operation. address and data can only be latched when the eepgm bit is at ?ero? reset and power-on reset, reset the eelat bit. eepgm ?eeprom programming power enable eepgm must be written to enable (or disable) the eepgm function. when set, eepgm turns on the charge pump and enables the programming (or erasing) power to the eeprom array. when clear, power is switched off. this enables pulsing of the programming voltage to be controlled internally. this bit can be read at any time, but can only be set if eelat=1. if eelat is not set, then eepgm cannot be set. eelat=0 or reset clears the eepgm bit. 13.4 eeprom options register (eeopr) this register contains the secure and protect functions for the eeprom and allows the user to select options in a non-volatile manner. the contents of the eeopr register are loaded into data latches with each power-on or external reset. the register is implemented in eeprom, therefore reset has no effect on the individual bits. $0400 bit 7 654321 bit 0 read: eeprt write: reset: 00000000 figure 13-2. eeprom options register (eeopr)
non-disclosure agreement required eeprom general release speci?ation mc68hc(7)05h12 ? rev. 1.0 156 eeprom motorola eeprt ?eeprom protect bit in order to achieve a higher degree of protection, the eeprom is split into two 128-byte blocks. block 1 cannot be protected. block 2 is protected by the eeprt bit of the options register. when this bit is set from 0 to 1 (erased), the protection remains until the next power-on or external reset. eeprt can only be written to ??when the elat bit in the eeprom control register is set. 1 = block 2 of the eeprom array is not protected; all 256 bytes of eeprom can be accessed for any read, erase or programming operations 0 = block 2 of the eeprom array is protected; any attempt to erase or program a location will be unsuccessful 13.5 eeprom read, erase and programming procedures 13.5.1 read procedure to read data form eeprom, the eelat bit must be clear. eepgm, eer1 and eer0 are all forced to zero. eeprom is read as if it were a normal rom. the charge pump generator is off since eepgm is zero. if a read is performed while elat is set, data will be read as $ff. 13.5.2 erase procedure there are three types of erase operation mode see table 13-1 , byte erase, block erase or bulk erase. to erase a byte of eeprom: set eelat = 1, er1 = 0 and er0 = 1, write to the address to be erased, and set eepgm for a time t ebyte . to erase a block of eeprom: set eelat = 1, er1 = 1 and er0 = 0, write to any address in the block, and set eepgm for a time t ebloc . for a bulk erase: set eelat = 1, er1 = 1, and er0 = 1, write to an address in the array with a0 or a1 = ?? and set eepgm for a time t ebulk .
eeprom operation in wait mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola eeprom 157 non-disclosure agreement required 13.5.3 programming procedure to program the content of eeprom, set eelat bits, write data to the desired address, and set the eepgm bit. after the required programming delay t eepgm , eelat must be clear, which also resets eepgm. during a programming operation, any access to eeprom will return $ff. to program a second byte, eelat must be cleared before it is set, or the programming will have no effect. note: each byte must be erased before reprogramming. do not use over- programming (write more ?eros?. 13.6 operation in wait the user may want to ensure that the rc oscillator is disabled before entering wait mode to help conserve power.
non-disclosure agreement required eeprom general release speci?ation mc68hc(7)05h12 ? rev. 1.0 158 eeprom motorola
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola pulse width modulator (pwm) 159 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 14. pulse width modulator (pwm) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.3.1 pwm channel microshifting . . . . . . . . . . . . . . . . . . . . . . . 161 14.4 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.4.1 pwm data registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.4.2 pwm control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.4.3 pwm channel enable register. . . . . . . . . . . . . . . . . . . . . 165 14.4.4 pwm channel polarity register . . . . . . . . . . . . . . . . . . . . 165 14.5 pwm during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.2 introduction the pulse width modulator (pwm) system has eight 8-bit channels. preceding the 8-bit ( ? 256) pwm counter is a programmable prescaler.the pwm frequency is selected by choosing the desired divide option from the programmable prescaler. the four pwm channels 0 to 3 provide four full h-bridge drivers capable of driving air core instruments or stepper motor instruments. each of the h-bridges will be implemented as a combination of one pwm power driver and another general purpose output (gpo) port power driver. a single pwm channel provides a pulse width ratio for the corresponding pwm driver part of a single h-bridge. thus the current through the bridge can be controlled by the pulse width ratio. the four pwm channels 4 to 7 with their power drivers can support four 90 (small angle) aircore instruments.
non-disclosure agreement required pulse width modulator (pwm) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 160 pulse width modulator (pwm) motorola figure 14-1. pwm block diagram (one channel) 14.3 functional description the pwm is capable of generating signals from 0% to 100% duty cycle. a $00 in the pwm data register yields an ?ow?output (0%), but a $ff yields a duty of 255/256. to achieve the 100% duty (?igh?output), the polarity control bit is set to zero while the data register has $00 in it. figure 14-1 shows the block diagram of a pwm timer channel 0 to 3. the 8-bit counter runs at the rate of the selected clock source provided by the programmable prescaler. the counter is compared to the data register. when the counter matches the data register a flip-flop changes state causing the pwm output to also change state. when the pwm counter rolls over it resets the flip-flop and the output changes back. notice that there is a select bit called ppol which allows each channel to independently create a signal which is a low-to-high or high-to-low transition. f op pwmc0 pwmc1 hc05 data bus ppol ? 0.5,1,2,4,64 prescaler 8-bit counter ( ?256) 8-bit comparator pwm data register buffer pwm data s r q q m u x pwm control, channel enable and channel polarity registers pwmc2 q q m u x left right sign pwme gpo gpo
pulse width modulator (pwm) functional description mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola pulse width modulator (pwm) 161 non-disclosure agreement required the sign bit in the pwm control register selects whether the left or the right port line (left or right path of an h-bridge) is enabled for the pwm signal. the opposite port line drives the general purpose output value. the sign bit performs also the inversion of the pwm signal. this is done because the duty values are assumed to be 2? complement values in the range from ?56 to +255. a change from duty value $01ff to value $0000 (? to 0) causes a change of the current direction within the corresponding h-bridge. this is done by changing the polarity of the pwm signal and exchanging pwm and output port signals within the h- bridge. 14.3.1 pwm channel microshifting switching more than one pwm channel simultaneously would cause large currents in the corresponding power drivers of the h-bridges. clocking of different channels must be delayed such that only one channel switches at a time. therefore microshifts are introduced to achieve a switching delay between different channels. figure 14-2. pwm microshifts 7/4t bus clock channel 0 channel 1 channel 7 channel 2 1/4t 2/4t bus bus bus
non-disclosure agreement required pulse width modulator (pwm) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 162 pulse width modulator (pwm) motorola the start of the pwm period is shifted by a quarter of the period time of the bus clock t bus for the channels 0 to 7. see figure 14-2 . inevitable large currents due to switching of the power drivers are distributed over a number of time slots. they do not load power supply at the same time. 14.4 registers associated with the pwm system, there are eight pwm data registers, a control/sign register, a channel enable register and a channel polarity register. the registers can be written to and read at any time. for updating the pwm values, the following sequence must be followed: 1. write the corresponding sign bit in the pwm control register 2. write data to the corresponding data register not until after the data register is written are the sign bits transferred from a buffer to the sign register. data written to a data register is held in a buffer and transferred to the pwm data register at the end of a pwm cycle. reads of a data register will always result in the read of the pwm data buffer and not the pwm data register.
pulse width modulator (pwm) registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola pulse width modulator (pwm) 163 non-disclosure agreement required 14.4.1 pwm data registers the pwm system has eight 8-bit data registers which hold the duty cycle for each pwm output. the data bits in these registers are set by reset. bit 7 654321 bit 0 pwm0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0010 write: pwm1 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0011 write: pwm2 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0012 write: pwm3 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0013 write: pwm4 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0014 write: pwm5 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0015 write: pwm6 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0016 write: pwm7 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0017 write: reset: 11111111 figure 14-3. pwm data registers (pwm0?)
non-disclosure agreement required pulse width modulator (pwm) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 164 pulse width modulator (pwm) motorola 14.4.2 pwm control register pwmrst ?pwm reset writing ??to the pwmrst bit resets the pwm counter. the pwmrst bit reads always as ?? pwmc3? ?pwm clock rate these bits select the input clock rate and determines the period as shown in figure 14-1 . the pwm prescaler clock input is f op , which is the bus frequency. sign3? ?sign of the pwm channel 0? the sign bit selects whether the left or the right output is the pwm signal. the opposite output is the general purpose port. the sign bit performs also the inversion of the pwm signal. see figure 7-4 for the assignment of the pwm channels to the power driver lines. 1 = right pwm output 0 = left pwm output $0018 bit 7 654321 bit 0 read: 0 pwmc3 pwmc2 pwmc1 sign3 sign2 sign1 sign0 write: pwmrst reset: 0 1110000 figure 14-4. pwm control register (pwmctl) table 14-1. pwm clock rate pwmc3 pwmc2 pwmc1 pwm clock pwm out 0 0 0 2 x f op f op / 128 001f op f op / 256 010f op / 2 f op / 512 011f op / 4 f op / 1024 100f op / 64 f op / 16384 101 pwm shut off - to save power if the pwm is not used 110 111
pulse width modulator (pwm) registers mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola pulse width modulator (pwm) 165 non-disclosure agreement required 14.4.3 pwm channel enable register pwme7? ?pwm channel enable these bits enable/disable the corresponding pwm channels. if a bit is disabled, the corresponding pin functions as a general purpose output (gpo). refer to section 7.7 port e and port f (power drivers) . 1 = the pwm channel is enabled. 0 = the pwm channel is disabled and the corresponding lines are general purpose outputs (gpo) 14.4.4 pwm channel polarity register ppol7? ?pwm polarity these bits initialize the corresponding pwm outputs. 1 = pwm channel is high at the beginning of the period, then toggles to low when the data count is reached. 0 = pwm channel is low at the beginning of the period, then toggles to high when the data count is reached. $0019 bit 7 654321 bit 0 read: pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 write: reset: 0 0000000 figure 14-5. pwm channel enable register (pwmen) $001a bit 7 654321 bit 0 read: ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 write: reset: 0 0000000 figure 14-6. pwm channel polarity register (pwmpol)
non-disclosure agreement required pulse width modulator (pwm) general release speci?ation mc68hc(7)05h12 ? rev. 1.0 166 pulse width modulator (pwm) motorola 14.5 pwm during wait mode the pwm continues normal operation during wait mode. to decrease power consumption during wait, the pwm should be shut off prior to entering wait mode by setting the corresponding bits in the pwm control register. refer to section 7.8 port e and port f during wait mode for information about the corresponding ports.
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola eprom 167 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 15. eprom 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.3 eprom bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.3.1 bootloader functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.4 eprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.4.1 eprom programming register (eprog) . . . . . . . . . . . . 170 15.5 mask option register (mor) . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.2 introduction the hc705h12 contains 12k eprom instead of rom and the mask options are controlled by a programmable nonvolatile mask option register (mor). the mor is an eprom register which must be programmed appropriately prior to operation of the micro-controller. 15.3 eprom bootloader bootloader programming mode is entered upon the rising edge of reset if the irq /v pp pin is at v tst and the pb0 pin is at logic one (refer to table 6-1 ). the bootloader code resides in the rom from $3f00 to $3fef. this program handles copying of user code from an external eprom into the on-chip eprom. the user code must be a one-to-one correspondence with the internal eprom addresses (including the mor).
non-disclosure agreement required eprom general release speci?ation mc68hc(7)05h12 ? rev. 1.0 168 eprom motorola 15.3.1 bootloader functions two pins are used to select various bootloader functions. these pins are pb2 and pb3. two other pins, pb7 and pb6 are used to drive the prog led and the verf led respectively. the programming modes are shown in table 15-1 . the bootloader uses an external 14 bit counter to address the memory device containing the code to be copied. this counter requires a clock (provided at pb5) and a reset signal (provided at pb4). note: the eprom must be erased before performing a program cycle. for the communication with a host computer via a standard rs-232 interface pb1 is used as transmitter (tx) and pb0 is used as receiver (rx). table 15-1. bootloader functions pb2 pb3 mode 0 0 program/verify eprom 0 1 verify only 1 0 jump to ram 1 1 load ram and execute
eprom eprom bootloader mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola eprom 169 non-disclosure agreement required figure 15-1. mc68hc705h12 programming circuit mc74hc393 27128 (16k eprom) +5v +5v +5v +5v s2 +5v 10k 470 10k +5v 470 s3 +5v 10k vpp 20 pf 1mhz l1 l2 mc68hc705h12 s1 +5v 10k pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 d0 d1 d2 d3 d4 d5 d6 d7 irq/vpp oe vss vss osc2 osc1 vdd vrefh avdd tcap0 pb3 pb2 reset pb5 pb4 clock reset pb7 pb6 l1 ?verify l2 ?program a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 vss clk rst vdd vcc vpp pgm 20 pf tcap1 tcap2 tcap2 ce
non-disclosure agreement required eprom general release speci?ation mc68hc(7)05h12 ? rev. 1.0 170 eprom motorola 15.4 eprom programming the eprom array is programmed through manipulation of the programming register located at $001d. it may be programmed in user, bootstrap or test mode. in addition to the main eprom array, the mask option register must also be programmed appropriately by the programming software. 15.4.1 eprom programming register (eprog) elat ?eprom latch control this read/write bit controls the latching of the address and data buses when programming the eprom. 1 = address and data buses are latched when the following instruction is a write to one of the eprom locations. normal reading is disabled if elat =1 0 = eprom address and data buses are configured for normal reading epgm ?eprom program control this read/write bit controls whether the programming voltage is applied to the eprom array. for programming, this bit can only be set if the latch bit has been previously set. both epgm and elat cannot be set in the single write. 1 = programming voltage applied to eprom array 0 = programming voltage not applied to eprom array $001d bit 7 654321 bit 0 read: elat epgm write: reset: 00000000 figure 15-2. eprom programming register (eprog)
eprom mask option register (mor) mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola eprom 171 non-disclosure agreement required the sequence for programming the eprom is as follows: 1. set the elat bit. 2. write the data to be programmed to the eprom (or mor byte) location to be programmed. 3. set the epgm bit. 4. wait a time t epgm 5. clear the elat and epgm bits. 6. repeat for each byte. 15.5 mask option register (mor) the mask option register (mor) is used to select all mask options available on the mc68hc705h12. when in the erased state, the eprom cells read as a logic zero which therefore represents the value transferred from the mor at reset if it is left unprogrammed. the unimplemented bits of this register are read as ?? there are two mask option registers (mor1, mor2) implemented. mor2 is used only. pwdrw ?ports e/f in wait mode 1 = ports e/f continue in wait (enabled) 0 = ports e/f are forced ?ow?in wait (disabled) cope ?cop timer enable 1 = cop timer enabled. 0 = cop timer disabled. bit 7 654321 bit 0 mor1 read: $3efe write: mor2 read: pwdrw cope $3eff write: reset: 00000000 figure 15-3. mask options registers (mor1 and mor2)
non-disclosure agreement required eprom general release speci?ation mc68hc(7)05h12 ? rev. 1.0 172 eprom motorola
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola electrical characteristics 173 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 16. electrical characteristics 16.1 contents 16.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 16.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 16.4 power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 16.5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 176 16.6 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 16.7 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . 178 16.8 eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.9 eprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.10 power driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.11 power-on reset/low voltage reset characteristics . . . . . . . 181
non-disclosure agreement required electrical characteristics general release speci?ation mc68hc(7)05h12 ? rev. 1.0 174 electrical characteristics motorola 16.2 maximum ratings (voltage referenced to v ss ) 1. only one output shorted for a time. stresses above those listed as ?aximum ratings?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that vin and vout be constrained to the range vss (vin or vout) vdd. unused inputs are connected to the appropriate voltage level, either vss or vdd. positive current flow is defined as conventional current flow into the device. negative current flow is defined as current flow out of the device. rating symbol value unit supply voltage v dd ?.3 to +7.0 v supply voltage for power drivers pv dd1,2 ?.3 to +10.0 v input voltage normal operation monitor mode (irq pin only) v in v in v ss ?0.3 to v dd + 0.3 v ss ?0.3 to 2 v dd + 0.3 v v current drain per pin i omax 300 ma short circuit time for power drivers (pe7?, pf3?) (note 1) t sc 20 ms operating temperature range t a ?0 to +85 c storage temperature range t stg ?5 to +150 c write/erase cycles eeprom 10,000 cycles data retention eeprom 10 years
electrical characteristics thermal characteristics mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola electrical characteristics 175 non-disclosure agreement required 16.3 thermal characteristics 16.4 power considerations the average chip junction temperature, t j , in degrees celsius can be obtained from the following equation: [1] where: t a = ambient temperature ( c) q ja = package thermal resistance, junction-to-ambient ( c/w) p d = p int + p i/o (w) p int = internal chip power = i dd ?v dd (w) p i/o = power dissipation on input and output pins (user determined) an approximate relationship between p d and t j (if p i/o is neglected) is: [2] solving equations [1] and [2] for k gives: [3] where k is a constant for a particular part. k can be determined by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained for any value of t a by solving the above equations. the package thermal characteristics are shown in section 16.3 thermal characteristics . characteristic symbol value unit thermal resistance plcc(52 pin) q ja 50 c / w t j t a p d q ja () + = p d k t j 273 + ---------------------- - = kp d t a 273 + () q ja p d 2 + =
non-disclosure agreement required electrical characteristics general release speci?ation mc68hc(7)05h12 ? rev. 1.0 176 electrical characteristics motorola 16.5 dc electrical characteristics (v dd = 5.0vdc 10%, v ss = 0vdc, t a = ?0 c to +85 c, unless otherwise noted) characteristic symbol min typ 1 max unit output voltage i load = ?0 m a i load = +10 m a v oh v ol v dd ?0.1 0.1 v output high voltage i load = ?.8 ma pa7?, pb7?, pc7? i load = ?0 m a osc2 v oh v dd ?0.8 v dd ?0.8 v v output low voltage i load = 1.6 ma pa7?, pb7?, pc7?, reset i load = 80 m a osc2 v ol 0.4 0.4 v v output source current (see maximum ratings) v o = 4.5 v (v dd = 5v) v o = 4.0 v (v dd = 5v) pa7?, pb7?, pc7? i oh ?.0 ?.0 ?4.5 ?6.0 ma ma output sink current (see maximum ratings) v o = 0.5 v (v dd = 5v) v o = 1.0 v (v dd = 5v) pa7?, pb7?, pc7? i ol 5.0 10.0 15.0 27.0 ma ma input high voltage pa7?, pb7?, pc7?, pd3?, irq , reset , osc1 v ih 0.7 v dd ? dd v input low voltage pa7?, pb7?, pc7?, pd3?, irq , reset , osc1 v il v ss 0.2 v dd v supply current (note 2) run (f op = 2.1 mhz) run (f op = 525 khz, slow mode) wait (f op = 2.1 mhz) wait (f op = 525 khz, slow mode) idd idd idd idd 7 3 1 10 7 6 4 ma ma ma ma io ports hi-z leakage current pa7?, pb7?, pc7? i il 1 m a input current pd3?, irq , osc1, v refh i in 1 m a
electrical characteristics dc electrical characteristics mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola electrical characteristics 177 non-disclosure agreement required 1. typical values re?ct average measurements at midpoint of voltage range at 25 c. 2. test conditions: all i/o ports are con?ured as output with no dc load. external clock input osc1 is driven by square wave external clock. 3. a simple protection can be built with a series resistor: r > v max /i inj the sum of currents during multiple injection should be limited below the maximum values for a single pin: r > (v max /i inj )?number of pins). the a/d conversion accuracy can degrade to 7lsb on a channel adjacent to the one subjected to current injection. not production tested. 4. the enabling of the lvr by mask option will cause a permanent current trough the lvr circuitry. 5. the mcu retains ram contents and cpu register contents. schmitt trigger inputs ?hysteresis pa7?, pb7?, pc6, pc3?, irq , reset v hyrs 0.3 1.5 v internal pullup resistor reset r rstpu 81114k w injection current (note 3) pa7? pb7? pc7? pd3? pe7? pf3? i inj 10 10 10 1 10 10 ma data retention supply voltage (note 5) v dr 2v oscillator transconductance (i osc2 /v osc1 )g m 1.1 ma/v characteristic symbol min typ 1 max unit
non-disclosure agreement required electrical characteristics general release speci?ation mc68hc(7)05h12 ? rev. 1.0 178 electrical characteristics motorola 16.6 control timing (v dd = 5.0vdc 10%, v ss = 0vdc, t a = ?0 c to +85 c, unless otherwise noted) 16.7 a/d converter characteristics 1. the minimum period tilil should not be less than the number of cycle times it takes to execute the interrupt ser- vice routine plus 21 t cyc . (v dd = 5.0vdc 10%, v ss = 0vdc, t a = ?0 c to +85 c, unless otherwise noted) characteristic symbol min max unit oscillator frequency crystal / ceramic resonator external clock source f osc dc 4.2 4.2 mhz mhz internal operating frequency (f osc / 2) crystal / ceramic resonator external clock f op dc 2.1 2.1 mhz mhz cycle time (1 / f op )t cyc 476 ns reset pulse width t rl 1.5 t cyc irq interrupt pulse width low (edge-triggered) t ilih 120 ns irq interrupt pulse period t ilil (1) ? cyc osc1 pulse width t oh ,t ol 100 ns characteristic parameter min max unit resolution number of bits resolved by the a/d 8 bit monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed quantization error uncertainly due to converter resolution 1/2 lsb offset error dc shift of the entire transfer curve of an ideal converter (1) 1/2 lsb gain error difference between the actual and expected gain (end point to end point) (1) 1/2 lsb differential linearity error difference between the actual analog voltage change and the ideal voltage change (1) 1/2 lsb integral linearity error max deviation from the best straight line through the a/d transfer characteristics (1) 1/2 lsb
electrical characteristics eeprom characteristics mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola electrical characteristics 179 non-disclosure agreement required 16.8 eeprom characteristics 1. avdd = v refh = vdd and v refl = 0 v 2. for 8-bit resolution vref 3 3.5v is necessary 3. when vin > v refh conversion result will be ?f?(for the max input voltage vin see maximum ratings) (v dd = 5.0vdc 10%, v ss = 0vdc, t a = ?0 c to +85 c, unless otherwise noted) absolute accuracy / total unadjusted error difference between the actual input voltage and the full-scale equivalent of the binary code output for all errors (1) 1.5 lsb conversion range analog input voltage range v ss v refh v v refh analog reference voltage (2) v ss vdd + 0.1 v conversion time total time to perform a single analog to digital conversion 32 cycles zero input reading conversion result when vin = v ss 00 hex full scale reading (3) conversion result when vin = v refh ff hex rc oscillator stabilization time t rcon 5 m s adc stabilization time t adon 100 m s characteristic parameter min max unit characteristic symbol min max unit eeprom byte programming time t eepgm 10 10 ms eeprom byte erase time t ebyte 10 10 ms eeprom block erase time t ebloc 10 50 ms eeprom bulk erase time t ebulk 20 50 ms rc oscillator stabilization time t rcon ? m s
non-disclosure agreement required electrical characteristics general release speci?ation mc68hc(7)05h12 ? rev. 1.0 180 electrical characteristics motorola 16.9 eprom characteristics (v dd = 5.0vdc 10%, v ss = 0vdc, t a = ?0 c to +85 c, unless otherwise noted) 1. typical value = 12 ?15 v. 16.10 power driver characteristics (all voltages are referenced to v ss , v dd = 5.0vdc 10%, v ss = 0vdc, t a = ?0 c to +85 c, inductive load at the power drivers outputs (pe7?,pf3?): l=100 mh, r=260 w ) 1. the value for the supply voltage for the power driver is under normal operating conditions as well as under short circuit conditions. 2. the power driver outputs are slew rate limited. the value show the minimal time for an inductive load (l=100 mh, r=260 w ) which is connected to pvdd. characteristic symbol min max unit eprom programming voltage rate 1 v pp v ss ?.3 17.5 v eprom programming time t epgm 4-ms eprom data retention 10 years characteristic symbol min typ max unit operating supply voltage for power drivers (1) pv dd v dd 9.5 v output high voltage i oh = ?5 ma pe7?, pf3? v oh pv dd ?0.5 pv dd + 0.5 v output low voltage i ol = +35 ma pe7?, pf3? v ol 0 0.5 v output rise time (2) 10% to 90% of v oh , pvdd = 8v, t = +25 c pe7?, pf3? t r 21 ns output fall time (note 2) 90% to 10% of v oh , pvdd = 8v, t = +25 c pe7?, pf3? t f 19 ns
electrical characteristics power-on reset/low voltage reset characteristics mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola electrical characteristics 181 non-disclosure agreement required 16.11 power-on reset/low voltage reset characteristics (v dd = 5.0vdc 10%, v ss = 0vdc, t a = ?0 c to +85 c, unless otherwise noted) 1. typical values re?ct average measurements at midpoint of voltage range at 25 c. characteristic symbol min typ (1) max unit low voltage reset (lvr) ?threshold voltage v ron ?(vdd increasing) v roff ?(vdd decreasing) hysteresis v ron v roff v hyst 3.4 3.3 0.1 3.85 3.75 4.3 4.2 v v v minimum reset voltage v min 1.0 v supply voltage rise and fall time 1000 ms low voltage reset internal delay time 5 ms
non-disclosure agreement required electrical characteristics general release speci?ation mc68hc(7)05h12 ? rev. 1.0 182 electrical characteristics motorola
mc68hc(7)05h12 ? rev. 1.0 general release speci?ation motorola mechanical specifications 183 non-disclosure agreement required general release specification ?mc68hc(7)05h12 section 17. mechanical specifications 17.1 contents 17.2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 17.3 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 17.2 pin assignments figure 17-1. 52-pin plcc pin assignments 40 46 8 14 21 27 7 1 47 34 20 33 vrefh avdd vdd pc0/tcap0 pc1/tcap1 pc2/tcap2 pc3/tcap3 pc4/tcmp0 pc5/tcmp1 pc6/rdi pc7/tdo pvdd2 pvss2 pe7 pe6 pe5 pe4 pf3 pf2 pf1 pf0 pe3 pe2 pe1 pe0 pvss1 pb3 pb2/eclk pb1 pb0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pvdd1 pd3/an3 pd2/an2 pd1/an1 pd0/an0 vss reset osc1 osc2 irq /vpp pb7/sck pb6/mosi pb5/miso pb4
non-disclosure agreement required mechanical speci?ations general release speci?ation mc68hc(7)05h12 ? rev. 1.0 184 mechanical specifications motorola 17.3 package dimensions figure 17-2. 52-pin plcc package dimensions ? ? ? ? pin 1 pin 52 v w y brk z r a c j e g g1 u b g1 z1 x 0.10 ? seating plane 0.18 t n ? l m m s s s s case no. 778-02 52 lead plcc dim. min. max. notes dim. min. max. a 19.94 20.19 1. datums ?? ?? ??and ??are determined where top of lead shoulder exits plastic body at mould parting line. 2. dimension g1, true position to be measured at datum ??(seating plane). 3. dimensions r and u do not include mould protrusion. allowable mould protrusion is 0.25mm per side. 4. dimensions and tolerancing per ansi y 14.5m, 1982. 5. all dimensions in mm. u 19.05 19.20 b 19.94 20.19 v 1.07 1.21 c 4.20 4.57 w 1.07 1.21 e 2.29 2.79 x 1.07 1.42 f 0.33 0.48 y 0.50 g 1.27 bsc z 2 10 h 0.66 0.81 g1 18.04 18.54 j 0.51 k1 1.02 k 0.64 z1 2 10 r 19.05 19.20 0.18 t l ? n p m s s s s 0.18 t l ? n p m s s s s 0.18 t n ? l m m s s s s 0.25 t l ? n p s s s s s
mc68hc(7)05h12 ? rev. 1.0 general release specification motorola index 185 general release specification ?mc68hc(7)05h12 index 16-bit timer block diagram 104 interrupts 64 register addresses 105 52-pin plcc case outline 184 52-pin plcc package 20 , 183 8-bit timer see core timer a a/d channel assignments 147 clock selection 147 conversion accuracy 150 data register (addr) 148 electrical characteristics 178 errors 151 status and control register (adscr) 146 , 147 accumulator 39 address mark wake-up 131 addressing modes 42 adon bit in adscr 146 adrc bit in adscr 146 alu ?arithmetic/logic unit 42 an0?n3 23 analog input 148 analog to digital converter see a/d avdd 21 b bit manipulation instructions 50 block diagrams 16-bit timer 104 core timer 98 mc68hc(7)05h12 19 pwm 160 sci 128 spi 119 bootloader 167 c carry/borrow flag 41 c-bit in ccr 41 ch3_0 bits in adscr 147 channel microshifting 161 co2e bit in tcr2 112 coco bit in adscr 146 coie bit in tcr1 111 condition code register (ccr) 40 control instructions 51 control timing 178 cop register (copr) 72 reset 70 , 101 cope bit in mor 171 copr bit in copr 72 core timer block diagram 98 counter register (ctcr) 101 interrupts 64
mc68hc(7)05h12 ? rev. 1.0 general release specification motorola index 186 index status and control register (ctscr) 99 counter 105 cpha bit in spcr 122 cpol bit in spcr 122 cross coupled coils 85 d data retention mode 78 dc electrical characteristics 176 differential linearity error 151 direct addressing mode 43 dod bit in spcr 121 e eclk bit in syscr 34 eclk pin 22 edge7? bits in paied 81 eelat bit in eepcr 155 eeosc bit in eepcr 154 eepgm bit in eepcr 155 eeprom 35 control register (eepcr) 154 , 155 electrical characteristics 179 erase 156 options register (eeopr) 155 , 156 programming 157 read 156 eeprt bit in eeopr 156 eer1, eer0 bits in eepcr 154 elat bit in eprog 170 epgm bit in eprog 170 eprom 35 bootloader 167 electrical characteristics 180 programming 170 programming register (eprog) 170 erase mode select 154 extended addressing mode 43 external interrupt 63 f fe bit in scsr 139 features 18 flowcharts interrupt 62 wait 77 g gain scale error 151 h half-carry flag 41 hardware interrupts 63 65 h-bit in ccr 41 h-bridge driver 86 states 90 with the pwm 94 i i/o programming 95 ic1f bit in tsr 113 ic2f bit in tsr 113 ici1e bit in tcr1 111 ici2e bit in tcr1 111 idle bit in scsr 139 idle line wake-up 131 iedg1 bit in tcr1 111 iedg2 bit in tcr1 111 ilie bit in sccr2 137 illegal address reset 72 immediate addressing mode 43 index register 39 indexed addressing mode 44
mc68hc(7)05h12 ? rev. 1.0 general release specification motorola index 187 index inherent addressing mode 43 input capture register 1 108 register 2 109 instruction types 45 integral linearity error 151 interrupts 16-bit timers 64 core timer 64 flowchart 62 hardware 63 irq 63 keyboard 63 sci 65 spi 65 swi 63 irq bit in syscr 34 irq pin 21 j jump/branch instructions 48 junction temperature, chip 175 k keyboard interrupt 22 , 63 , 80 l low power modes 65 , 76 low voltage reset (lvr) 72 electrical characteristics 181 m m bit in sccr1 136 mask options 20 register (mor) 171 master mode 120 maximum ratings 174 memory map 26 miso 22 , 116 modes of operation data retention 78 entry conditions 75 low power (wait) 65 , 76 78 monitor 76 slow 78 user 75 monitor mode 76 monitor rom 35 monotonicity 150 mor 171 mosi 22 , 117 mstr bit in spcr 121 n n-bit in ccr 41 negative flag 41 nf bit in scsr 139 o oc1f bit in tsr 113 oc2f bit in tsr 114 oci1e bit in tcr1 111 oci2e bit in tcr2 112 offset error 151 olvl1 bit in tcr1 111 olvl2 bit in tcr2 112 opcode map 58 operating modes see modes of operation or bit in scsr 139 osc1, osc2 21 oscillator pins 21 output compare 106
mc68hc(7)05h12 ? rev. 1.0 general release specification motorola index 188 index register 1 106 register 2 107 p pa0?a7 22 paie7? bits in paicr 81 paif7? bits in paisr 82 pb0?b7 22 pc0?c7 22 pd0?d3 23 pe0?e7 23 pf0?f3 23 pins an0?n3 23 assignments 20 avdd 21 eclk 22 irq 21 keyboard interrupt 22 miso 22 mosi 22 osc1, osc2 21 port a (pa0?a7) 22 port b (pb0?b7) 22 port c (pc0?c7) 22 port d (pd0?d3) 23 port e (pe0?e7) 23 port f (pf0?f3) 23 pvdd1, pvss1, pvdd2, pvss2 23 rdi 22 reset 21 sck 22 tcap0? 22 tcmp0? 22 tdo 22 vdd, vss 21 vpp 21 vrefh 23 port a interrupt control register (paicr) 81 interrupt edge register (paied) 81 interrupt status register (paisr) 82 keyboard interrupt 80 port b 82 port c 83 port d 83 port e and port f configurations 92 mismatch registers (pemism and pfmism) 89 , 90 power drivers 83 power considerations 175 power driver circuit 87 electrical characteristics 180 pins 23 , 83 power supply pins 21 power-on reset (por) 70 electrical characteristics 181 ppol7? bits in pwmpol 165 program counter 40 programming circuit 169 programming model 38 pulse width modulator see pwm pvdd1, pvss1, pvdd2, pvss2 23 pwdrw bit in mor 171 pwm block diagram 160 channel enable register (pwmen) 165 channel microshifting 161 channel polarity register (pwmpol) 165 control register (pwmctl) 164 data registers (pwm0?) 163 pwmc3? bits in pwmctl 164 pwme7? bits in pwmen 165
mc68hc(7)05h12 ? rev. 1.0 general release specification motorola index 189 index pwmrst bit in pwmctl 164 q quantization error 151 r r8 bit in sccri 136 ram 35 rckb bit in baud 141 rdi 22 rdrf bit in scsr 139 re bit in sccr2 138 read-modify-write instructions 47 receive data (rdi) 132 receiver 130 register/memory instructions 46 registers addr 148 adscr 146 baud 140 complete listing 29 33 copr 72 ctcr 102 ctscr 99 eeopr 155 eepcr 154 eprog 170 mor 171 paicr 81 paied 81 paisr 82 pemism 89 pfmism 90 pwm07 163 pwmctl 164 pwmen 165 pwmpol 165 sccr1 136 sccr2 137 scdat 135 scsr 138 spcr 121 spdat 124 spsr 123 summary 27 syscr 34 tcr1 110 tcr2 112 tsr 113 relative addressing mode 45 reset 21 , 67 resets computer operating properly (copr) 70 external 67 illegal address 72 internal 68 lvr 72 por 70 reset 67 rie bit in sccr2 137 rom 35 rrtif bit in ctscr 100 rt1, rt0 bits in ctscr 100 rti rates 100 rtie bit in ctscr 100 rtif bit in ctscr 99 rtof bit in ctscr 100 rwu bit in sccr2 138 s sbk bit in sccr2 138 sc bit in syscr 34 sci baud rate register (baud) 140 , 141 block diagram 128
mc68hc(7)05h12 ? rev. 1.0 general release specification motorola index 190 index control register 1 (sccr1) 136 control register 2 (sccr2) 137 , 138 data format 130 data register (scdat) 135 interrupt 65 receiver wake-up 130 status register (scsr) 138 , 139 sck 22 , 117 scp1, scpo bits in baud 141 scr2, scr1, scro bits in baud 141 serial communcations interface see sci serial peripheral interface see spi short circuit detection 88 sign3? bits in pwmctl 164 slave mode 120 slow mode 78 software interrupt (swi) 63 spe bit in spcr 121 spi block diagram 119 control register (spcr) 121 , 122 data i/o register (spdat) 124 interrupt 65 master and slave 120 miso 116 mosi 117 serial clock (sck) 117 status register (spsr) 123 spie bit in spcr 121 spif bit in spsr 123 spp bit in baud 140 spr1, spr0 bits in spcr 122 stack pointer 39 start bit 132 system control register (syscr) 34 eclk ?internal system clock available 34 irq ?irq sensitivity 34 sc ?system clock option 34 t t8 bit in sccr1 136 tc bit in scsr 139 tcap0? 22 tcap1 bit in tsr 113 tcap2 bit in tsr 113 tcie bit in sccr2 137 tclr bit in baud 140 tcmp0? 22 tdo 22 tdre bit in scsr 139 te bit in sccr2 137 thermal characteristics 175 tie bit in sccr2 137 timer control register 1 (tcr1) 110 co1e ?timer compare 1 output enable 111 ici1e ?input capture 1 interrupt enable 111 ici2e ?input capture 2 interrupt enable 111 iedg1 ?input edge 111 iedg2 ?input edge 111 oci1e ?output compare 1 interrupt enable 111 olvl1 ?output level 1 111 toie ?timer overflow interrupt enable 111 timer control register 2 (tcr2) 112 co2e ?timer compare 2 output enable 112 oci2e ?output compare 2 interrupt enable 112 olvl2 ?output level 2 112 timer status register (tsr) 113 ic1f ?input capture 1 flag 113 ic1f ?output compare 1 flag 113 ic2f ?input capture 2 flag 113 ic2f ?output compare 2 flag 114 tcap1 ?timer capture 1 113
mc68hc(7)05h12 ? rev. 1.0 general release specification motorola index 191 index tcap2 ?timer capture 2 113 tof ?timer overflow flag 113 timing diagrams data clock 118 reset and por 69 tof bit in ctscr 99 tof bit in tsr 113 tofe bit in ctscr 100 toie bit in tcr1 111 total unadjusted error 151 transfer curve 150 transmit data (tdo) 135 u user mode 75 v vdd, vss 21 vector addresses 61 vpp 21 vrefh 23 w wait mode 65 , 77 wake bit in sccr1 136 wake-up 130 address mark 131 idle line 131 watchdog see cop wcol bit in spsr 123 z z-bit in ccr 41 zero flag 41
mc68hc(7)05h12 ? rev. 1.0 general release specification motorola index 192 index

hc05h12grs/d motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?mative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405; denver, colorado 80217.1-800-441-2447 or 303-675-2140 mfax: rmfax0@email.sps.mot.com ?touchtone 602-244-6609 internet: http://www.mot.com/sps/ japan: nippon motorola ltd.; tatsumi-spd-jldc, 6f seibu-butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan. 81-3-3521-8315 asia/pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298 mfax is a trademark of motorola, inc. motorola, inc., 1997

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